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부품번호 ADV7192 기능
기능 Video Encoder with Six 10-Bit DACs/ 54 MHz Oversampling and Progressive Scan Inputs
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ADV7192 데이터시트, 핀배열, 회로
a Video Encoder with Six 10-Bit DACs, 54 MHz
Oversampling and Progressive Scan Inputs
ADV7192
FEATURES
Six High-Quality 10-Bit Video DACs
10-Bit Internal Digital Video Processing
Multistandard Video Input
Multistandard Video Output
4؋ Oversampling with Internal 54 MHz PLL
Programmable Video Control Includes:
Digital Noise Reduction
Gamma Correction
Black Burst
LUMA Delay
CHROMA Delay
Multiple Luma and Chroma Filters
Luma SSAF™ (Super Subalias Filter)
Average Brightness Detection
Field Counter
Macrovision Rev. 7.1
CGMS (Copy Generation Management System)
WSS (Wide Screen Signaling)
Closed Captioning Support.
Teletext Insertion Port (PAL-WST)
2-Wire Serial MPU Interface (I2C®-Compatible
and Fast I2C)
I2C Interface
Supply Voltage 5 V and 3.3 V Operation
80-Lead LQFP Package
APPLICATIONS
DVD Playback Systems
PC Video/Multimedia Playback Systems
Progressive Scan Playback Systems
GENERAL DESCRIPTION
The ADV7192 is part of the new generation of video encoders
from Analog Devices. The device builds on the performance of
previous video encoders and provides new features like interfac-
ing progressive scan devices, Digital Noise Reduction, Gamma
Correction, 4× Oversampling and 54 MHz operation, Average
Brightness Detection, Black Burst Signal Generation, Chroma
Delay, an additional Chroma Filter, and other features.
The ADV7192 supports NTSC-M, NTSC-N (Japan), PAL N,
PAL M, PAL-B/D/G/H/I and PAL-60 standards. Input standards
supported include ITU-R.BT656 4:2:2 YCrCb in 8-Bit or 16-Bit
format and 3× 10-Bit YCrCb progressive scan format.
The ADV7192 can output Composite Video (CVBS), S-Video
(Y/C), Component YUV or RGB and analog progressive scan in
YPrPb format. The analog component output is also compatible
with Betacam, MII, and SMPTE/EBU N10 levels, SMPTE
170 M NTSC, and ITU–R.BT 470 PAL.
Please see Detailed Description of Features for more informa-
tion about the ADV7192.
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
DIGITAL
INPUT
27MHz
CLOCK
ITU–R.BT
656/601
8-BIT YCrCb
IN 4:2:2 FORMAT
VIDEO
INPUT
PROCESSING
VIDEO
SIGNAL
PROCESSING
VIDEO
OUTPUT
PROCESSING
PLL
AND
54MHz
DEMUX
AND
YCrCb-
TO-
YUV
MATRIX
COLOR CONTROL
DNR
GAMMA
CORRECTION
VBI
TELETEXT
CLOSED CAPTION
CGMS/WSS
CHROMA
LPF
SSAF
LPF
LUMA
LPF
2؋
OVERSAMPLING
OR
4؋
OVERSAMPLING
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
I2C INTERFACE
ADV7192
ANALOG
OUTPUT
COMPOSITE VIDEO
Y [S-VIDEO]
C [S-VIDEO]
RGB
YUV
YPrPb
TV SCREEN
OR
PROGRESSIVE
SCAN DISPLAY
SSAF is a trademark of Analog Devices Inc.
This device is protected by U.S. patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights.
ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).
I2C is a registered trademark of Philips Corporation.
Throughout the document YUV refers to digital or analog component video.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000




ADV7192 pdf, 반도체, 판매, 대치품
ADV7192–SPECIFICATIONS
3.3 V SPECIFICATIONS1 (VAA = 3.3 V, VREF = 1.235 V, RSET1,2 = 1200 unless otherwise noted. All specifications TMIN to TMAX2
unless otherwise noted.)
Parameter
Min Typ Max
Unit
Test Conditions
STATIC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
10 Bits
1.0 LSB
1.0 LSB Guaranteed Monotonic
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current3
Input Leakage Current4
Input Current, IIN
Input Capacitance, CIN
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current5
Three-State Leakage Current6
Three-State Output Capacitance
2
0.8
1
200
±1
6 10
2.4
0.4
10
200
6 10
V
V
µA
µA
µA VIN = 0.4 V or 2.4 V
pF
V ISOURCE = 400 µA
V ISINK = 3.2 mA
µA
µA
pF
ANALOG OUTPUTS
Output Current (Max)
Output Current (Min)
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
4.125 4.33 4.625
2.16
0.4 2.5
1.4
100
6
mA RL = 300
mA RL = 600 , RSET1,2 = 2400
%
V
k
pF IOUT = 0 mA
VOLTAGE REFERENCE
Reference Range, VREF7
1.235
V IVREFOUT = 20 µA
POWER REQUIREMENTS
VAA
Normal Power Mode
IDAC (Max)8
ICCT (2× Oversampling)9, 10
ICCT (4× Oversampling)9, 10
IPLL
Sleep Mode
IDAC10
ICCT
3.15
3.3 3.6
29
42 54
68 86
6
0.01
85
V
mA
mA
mA
mA
µA
µA
NOTES
1All measurements are made in 4× Oversampling Mode unless otherwise specified and are guaranteed by characterization. In 2 × Oversampling Mode, power require-
ment for the ADV7192 is typically 3.0 V.
2Temperature range TMIN to TMAX: 0°C to 70°C.
3For all inputs but PAL_NTSC and ALSB.
4For PAL_NTSC and ALSB inputs.
5For all outputs but VSO/TTX/CLAMP.
6For VSO/TTX/CLAMP output.
7Measurement made in 2× Oversampling Mode.
8IDAC is the total current required to supply all DACs including the VREF Circuitry.
9All six DACs ON.
10ICCT or the circuit current, is the continuous current required to drive the digital core without I PLL.
Specifications subject to change without notice.
–4– REV. 0

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ADV7192 전자부품, 판매, 대치품
ADV7192
3.3 V TIMING CHARACTERISTICS (VAA = 3.3 V ؎ 150 mV, VREF = 1.235 V, RSET1,2 = 1200 unless otherwise noted. All
specifications TMIN to TMAX1 unless otherwise noted.)2
Parameter
Min Typ Max Unit
Test Conditions
MPU PORT
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
ANALOG OUTPUTS
Analog Output Delay
DAC Analog Output Skew
0
0.6
1.3
0.6
0.6
100
0.6 2
400
300
300
8
0.1
kHz
µs
µs
µs
µs
ns
ns
ns
µs
ns
ns
After This Period the First Clock Is Generated
Relevant for Repeated Start Condition
CLOCK CONTROL AND PIXEL
PORT 3
fCLOCK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Digital Output Access Time, t13
Digital Output Hold Time, t14
Pipeline Delay, t15 (2× Oversampling)
TELETEXT PORT4
Digital Output Access Time, t16
Data Setup Time, t17
Data Hold Time, t18
RESET CONTROL
RESET Low Time
27
82
83
64
4 2.0
2, 5
3
13
12
37
11
3
6
3
20
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
ns
ns
ns
ns
PLL
PLL Output Frequency
54 MHz
NOTES
1Temperature range TMIN to TMAX: 0°C to 70°C.
2Guaranteed by characterization.
3Pixel Port consists of:
Data: P7–P0, Y0/P8–Y7/P15 Pixel Inputs
Control: HSYNC, VSYNC, BLANK
Clock: CLKIN
4Teletext Port consists of:
Digital Output: TTXRQ
Data: TTX
Specifications subject to change without notice.
REV. 0
–7–

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