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PDF AIC1341 Data sheet ( Hoja de datos )
| Número de pieza | AIC1341 | |
| Descripción | High Performance/ Triple-Output/ Auto-Tracking Combo Controller | |
| Fabricantes | Analog Intergrations Corporation | |
| Logotipo |  |
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AIC1341
High Performance, Triple-Output, Auto-
Tracking Combo Controller
n FEATURES
l Provide Triple Accurate Regulated Voltages
l Optimized Voltage-Mode PWM Control
l Dual N-Channel MOSFET Synchronous Drivers
l Fast Transient Response
l Adjustable Over Current Protection using RDS(ON).
No External Current Sense Resistor Required.
l Programmable Softstart Function
l 200KHz Free-Running Oscillator
l Robust Outputs Auto-Tracking Characteristics
l Sink and Source Capabilities with External Circuit
n APPLICATIONS
l Advanced PC Mboards
l Information PCs
l Servers and Workstations
l Internet Appliances
l PC Add-On Cards
l DDR Termination
n GENERAL DESCRIPTION
The AIC1341 combines a synchronous voltage
mode PWM controller with two linear controllers
as well as the monitoring and protection functions
in this chip. The PWM controller regulates the
output voltage with a synchronous rectified step-
down converter. The built-in N-Channel MOSFET
drivers also help to simplify the design of step-
down converter. It is able to power CPUs, GPUs,
memories, chipsets and multi-voltage applications.
The PWM controller features over current protec-
tion using RDS(ON). It improves efficiency and saves
cost, as there is no expensive current sense resis-
tor required.
Two built-in adjustable linear controllers drive an
external MOSFETs to form two linear regulators
that regulates power for multiple system I/O. Out-
put voltage of both linear regulators can also be
adjusted by means of the external resistor divider.
Both linear regulators feature current limit. For a
system I/O requires current less than 500mA, the
AIC1340 is recommended for saving one external
MOSFET.
The programmable soft-start design provodes a
controlled output voltage rise, which limits the cur-
rent rate during power on time.
The shutdown function is also provided for dis-
abling the combo controller.
Analog Integrations Corporation 4F, 9, Industry E. 9th Rd, Science Based Industrial Park, Hsinchu Taiwan, ROC
DS-1341-00 May 24, 01
TEL: 886-3-5772500 FAX: 886-3-5772510
www.analog.com.tw
1
1 page  
AIC1341
n PIN DESCRIPTIONS
Pin 1:
PHASE: Over-current detection pin. Con-
nect the PHASE pin to source of
the external high-side N-
MOSFET. This pin detects the
voltage drop across the high-side
N-MOSFET RDS(ON) for over-
current protection.
Pin 2:
UGATE: External high-side N-MOSFET
gate drive pin. Connect UGATE
to gate of the external high-side
N-MOSFET.
Pin 3: SD:
To shut down the system, active
high or floating. If connecting a
resistor to ground, keep the re-
sistor less than 4.7K
Pin 4: VCC:
Pin 5: SS:
The chip power supply pin. It also
provides the gate bias charge for
all the MOSFETs controlled by
the IC. Recommended supply
voltage is 12V.
Soft-start pin. Connect a capaci-
tor from this pin to ground. This
capacitor, along with an internal
10µA (typically) current source,
sets the soft-start interval of the
converter.
Pulling this pin low will shut down
the IC.
Pin 6: FB2:
Connect this pin to a resistor di-
vider to set the linear regulator
output voltage.
Pin 7: VIN2:
This pin supplies power to the
internal regulator. Connect this
pin to a suitable 3.3V source.
Additionally, this pin is used to
monitor the 3.3V supply. If, fol-
lowing a start-up cycle, the volt-
age drops below 2.6V (typically),
the chip shuts down. A new soft-
start cycle is initiated upon re-
turn of the 3.3V supply above
the under-voltage threshold.
Pin 8:
GATE2: Linear Controller output drive pin.
This pin can drive either a Dar-
lington NPN transistor or a N-
channel MOSFET.
Pin 9: GND:
Signal GND for IC. All voltage
levels are measured with respect
to this pin.
Pin 10: GATE3: Linear Controller output drive pin.
This pin can drive either a Dar-
lington NPN transistor or an N-
channel MOSFET.
Pin 11: FB3
Negative feedback pin for the
linear controller error amplifier
connect this pin to a resistor di-
vider to set the linear controller
output voltage.
Pin 12: COMP1 External compensation pin. This
pin is connected to error ampli-
fier output and PWM comparator.
A RC network is connected to
FB1 to compensate the voltage
control feedback loop of the con-
verter.
Pin 13: FB1
The error amplifier inverting input
pin. The FB1 pin and COMP1 pin
are used to compensate the volt-
age-control feedback loop.
Pin 14: OCSET: Current limit sense pin. Connect
a resistor ROCSET from this pin to
the drain of the external high-side
N-MOSFET. ROCSET, an internal
200µA current source (IOCSET),
and the upper N-MOSFET on-
resistance (RDS(ON)) set the over-
current trip point according to the
following equation:
IPEAK = IOCSET × ROCSET
RDS(ON)
5
5 Page 
IRIPPLE = (VIN − VOUT) × VOUT ;
f × L × VIN
f = 200KHz oscillator frequency.
The inductor must be able to withstand peak cur-
rent without saturation, and the copper resistance
in the winding should be kept as low as possible
to minimize resistive power loss
Input Capacitor Selection
Most of the input supply current is supplied by the
input bypass capacitor, the resulting RMS current
flow in the input capacitor will heat it up. Use a
mix of input bulk capacitors to control the voltage
overshoot across the upper MOSFET. The ce-
ramic capacitance for the high frequency decou-
pling should be placed very close to the upper
MOSFET to suppress the voltage induced in the
parasitic circuit impedance. The buck capacitors
to supply the RMS current is approximate equal
to:
IRMS = (1− D) ×
D×
I2 OUT
+
1
12
×
VfIN××LD
2
, where D = VOUT
VIN
The capacitor voltage rating should be at least
1.25 times greater than the maximum input volt-
age.
PWM MOSFET Selection
In high current PWM application, the MOSFET
power dissipation, package type and heatsink are
the dominant design factors. The conduction loss
is the only component of power dissipation for the
lower MOSFET, since it turns on into near zero
voltage. The upper MOSFET has conduction loss
and switching loss. The gate charge losses are
proportional to the switching frequency and are
AIC1341
dissipated by the AIC1341. However, the gate
charge increases the switching interval, tSW, which
increase the upper MOSFET switching losses.
Ensure that both MOSFETs are within their
maximum junction temperature at high ambient
temperature by calculating the temperature rise
according to package thermal resistance specifi-
cations.
PUPPER = IOUT2 × RDS(ON) × D + IOUT × VIN × tSW × f
2
PLOWER = IOUT2 × RDS(ON) × (1− D)
The equations above do not model power loss due
to the reverse recovery of the lower MOSFET’s
body diode.
The RDS(ON) is different for the two previous equa-
tions even if the type devices is used for both.
This is because the gate drive applied to the upper
MOSFET is different than the lower MOSFET.
Logic level MOSFETs should be selected based
on on-resistance considerations, RDS(ON) should
be chosen base on input and output voltage, al-
lowable power dissipation and maximum required
output current. Power dissipation should be cal-
culated based primarily on required efficiency or
allowable thermal dissipation.
Rectifier Schottky diode is a clamp that prevent
the loss parasitic MOSFET body diode from con-
ducting during the dead time between the turn off
of the lower MOSFET and the turn on of the upper
MOSFET. The diode’s rated reverse breakdown
voltage must be greater than twice the maximum
input voltage.
Linear Controller MOSFET Selection
The power dissipated in a linear regulator is :
PLINEAR = IOUT × (VIN2 − VOUT)
Select a package and heatsink that maintains
junction temperature below the maximum rating
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet AIC1341.PDF ] | |
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