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PDF AIC1571CS Data sheet ( Hoja de datos )
| Número de pieza | AIC1571CS | |
| Descripción | 5-bit DAC/ Synchronous PWM Power Regulator with Dual Linear Controllers | |
| Fabricantes | Analog Intergrations Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AIC1571CS (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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AIC1571
5-bit DAC, Synchronous PWM Power
Regulator with Dual Linear Controllers
FEATURES
Provides 3 Regulated Voltages for Microproces-
sor Core, Clock and GTL Power.
Simple Voltage-Mode PWM Control.
Dual N-Channel MOSFET Synchronous Driver.
Operates from +3.3V, +5V and +12V Inputs.
Fast Transient Response.
Full 0% to 100% Duty Ratios.
±1.0% Output Voltage for VCORE and ±2.0%
Output Voltage Reference for VCLK and VGTL.
TTL Compatible 5-bit Digital-to-Analog Core Out-
put Voltage Selection. Range from 1.3V to 3.5V.
0.1V Steps from 2.1V to 3.5V.
0.05V Steps from 1.3V to 2.05V.
Adjustable Current Limit without External Sense
Resistor.
Microprocessor Core Voltage Protection against
Shorted MOSFET.
Power Good Output Voltage Monitor.
Over-Voltage and Over-Current Fault Monitors.
200KHz Free-Running Oscillator Programmable
up to 350KHz.
APPLICATIONS
Full Motherboard Power Regulation for Comput-
ers.
Power Integrations for 3 Output Power System.
DESCRIPTION
The AIC1571 combines a synchronous voltage
mode controller with two linear controllers as well
as the monitoring and protection functions in this
chip. The PWM controller regulates the microproc-
essor core voltage with a synchronous rectified
buck converter. One linear controller regulates
power for the GTL bus and the other linear con-
troller provides power for the clock driver circuit or
memory (1.8V)
An integrated 5 bit D/A converter that adjusts the
core PWM output voltage from 2.1V to 3.5V in 0.1V
increments and from 1.3V to 2.05V in 0.05V incre-
ments. The linear regulator uses an internal driver
device to provide 2.5V±2.5%. The linear controller
drives with an external N-channel MOSEFET to
provide 1.5V±2.5%.
This chip monitors all the output voltages. Power
Good signal is issued when the core voltage is
within ±10% of the DAC setting and the other levels
are above their under-voltage levels. Over-voltage
protection for the core output uses the lower N-
channel MOSFET to prevent output voltage above
115% of the DAC setting.
The PWM over-current function monitors the out-
put current by using the voltage drop across the
upper MOSFET’s RDS(on), eliminating the need for a
current sensing resistor.
Analog Integrations Corporation 4F, 9, Industry E. 9th Rd, Science Based Industrial Park, Hsinchu Taiwan, ROC
DS-1571-00 Oct 9, 00
TEL: 886-3-5772500 FAX: 886-3-5772510
www.analog.com.tw
1
1 page  
TYPICAL PERFORMANCE CHARACTERISTICS
UGATE
UGATE
AIC1571
LGATE
LGATE
FIG.1 The gate drive waveforms
60
CUGATE=CLGATE=CGATE
50 VCC=12V
40
30
20
10
CGATE=5000pF
CGATE=2000pF
CGATE=660pF
10000
1000
RT Pull Up to +12V
100
10
RT Pull Down to GND
0
100 150 200 250 300 350 400
Switching Frequency (KHz)
FIG. 2 Bias Supply Current VS. Frequency
1
100
150
200 250
300 350 400
Switching Frequency (KHz)
FIG. 3 RT Resistance VS. Frequency
450
PGOOD (5V/div)
VOUT1 (1V/div)
VOUT2 (1V/div)
VOUT3 (1V/div)
SS (2V/div)
SS (2V/div)
VOUT2 (1V/div)
PGOPOGDO(5OVD/di(v5)V/div)
SSSS(2(V2V/d/diivv)
VOUT3
VOUT3
VOUVTO1 U(1T1V(/1dVi/vd)iv)
FIG.4-1 Circuit 1---Soft Start Interval with 3 Outputs
and PGOOD
FIG.4-2 Circuit 2---Soft Start Interval with 3
Outputs and PGOOD
5
5 Page 
AIC1571
LUV
OC1
0.2V
SS
3.6V
OV
+
+
OVER CURRENT
LATCH
SQ
R
INHIBIT
S
COUNTER
R
POR
FAULT LATCH
S VCC
RQ
FAULT
Fig. 17 Simplified Schematic of Fault Logic
A simplified schematic is shown in figure 17. An
over-voltage detected on VSEN immediately
sets the fault latch. A sequence of three over-
current fault signals also sets the fault latch. An
under-voltage event on either linear output
(FB2 or FB3) is ignored until the soft-start inter-
val. Cycling the bias input voltage (+12V) off
then on reset the counter and the fault latch.
Over-Voltage Protection
During operation, a short on the upper PWM
MOSFET (Q1) causes VOUT1 to increase. When
the output exceed the over-voltage threshold of
115% of DACOUT, the FAULT pin is set to
fault latch and turns Q2 on as required in order
to regulate VOUT1 to 115% of DACOUT. The
fault latch raises the FAULT pin close to VCC
potential.
A separate over-voltage circuit provides pro-
tection during the initial application of power.
For voltage on VCC pin below the power-on re-
set (and above 4V), should VSEN exceed 0.7V,
the lower MOSFET (Q2) is driven on as need-
ed to regulate VOUT1 to 0.7V.
Over-Current Protection
All outputs are protected against excessive
over-current. The PWM controller uses upper
MOSFET’s on-resistance, RDS(ON) to monitor
the current for protection against shorted out-
puts. Both the linear regulator and controller
monitor FB2 and FB3 for under-voltage to pro-
tect against excessive current.
When the voltage across Q1 (ID•RDS(ON)) ex-
ceeds the level (200µA•ROCSET), this signal in-
hibit all outputs. Discharge soft-start capacitor
(Css) with 10µA current sink, and increments
the counter. Css recharges and initiates a soft-
start cycle again until the counter increments to
3. This sets the fault latch to disable all outputs.
Fig. 6 illustrates the over-current protection un-
til an over load on OUT1.
Should excessive current cause FB2 or FB3 to
fall below the linear under-voltage threshold,
the LUV signal sets the over-current latch if
Css is fully charged. Cycling the bias input
power off then on reset the counter and the
fault latch.
The over-current function for PWM controller
will trip at a peak inductor current (IPEAK) deter-
mined by:
IPEAK
=
IOCSET × ROCSET
RDS(ON)
The OC trip point varies with MOSFET’s tem-
perature. To avoid over-current tripping in the
normal operating load range, determine the
ROCSET resistor from the equation above with:
1. The maximum RDS(ON) at the highest junction.
2. The minimum IOCSET from the specification
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet AIC1571CS.PDF ] | |
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