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부품번호 | AK4112A 기능 |
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기능 | High Feature 96kHz 24-bit DIR | ||
제조업체 | Asahi Kasei Microsystems | ||
로고 | |||
전체 30 페이지수
ASAHI KASEI
[AK4112A]
AK4112A
High Feature 96kHz 24bit DIR
GENERAL DESCRIPTION
The AK4112A is a digital audio receiver (DIR) compatible with 96kHz, 24bits. The channel status
decoding supports both consumer and professional modes. The AK4112A can automatically detect a
Non-PCM bit stream. When combined with an AK4527 multi channel codec, the two chips provide a
system solution for AC-3 applications. The dedicated pins or a serial uP I/F can control the mode setting.
The small package, 28pin VSOP saves the board space.
*AC-3 is a trademark of Dolby Laboratories.
FEATURES
o Supports AES/EBU, IEC958, S/PDIF, EIAJ CP1201
o Low jitter Analog PLL
o PLL Lock Range : 22k~108kHz
o Clock Source: PLL or X'tal
o 4 channel Receivers input and 1 through transmission output
o Auxiliary digital input
o De-emphasis for 32kHz, 44.1kHz, 48kHz and 96kHz
o Dedicated Detect Pins
· Non-PCM Bit Stream Detect Pin
· Validity Flag Detect Pin
· 96kHz Sampling Detect Pin
· Unlock & Parity Error Detect Pin
o Supports up to 24bit Audio Data Format
o Audio I/F: Master or Slave Mode
o 32bits Channel Status Buffer
o Burst Preamble bit Pc, Pd Buffer for Non-PCM bit stream
o Serial µP I/F
o Two Master Clock Outputs:128fs/256fs/512fs
o Operating Voltage: 2.7 to 3.6V with 5V tolerance
o Small Package: 28pin VSOP
o Ta: -40~85°C
MS0020-E-00
-1-
2000/3
ASAHI KASEI
n Ordering Guide
AK4112AVF
n Pin Layout
-40 ~ +85 °C
28pin VSOP (0.65mm pitch)
[AK4112A]
DVDD
DVSS
TVDD
V/TX
XTI
XTO
PDN
R
AVDD
AVSS
RX1
RX2/DIF0
RX3/DIF1
RX4/DIF2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Top
View
28 CM0/CDTO
27 CM1/CDTI
26 OCKS1/CCLK
25 OCKS0/CSN
24 MCKO1
23 MCKO2
22 DAUX
21 BICK
20 SDTO
19 LRCK
18 ERF
17 FS96
16 P/SN
15 AUTO
MS0020-E-00
-4-
2000/3
4페이지 ASAHI KASEI
[AK4112A]
SWITCHING CHARACTERISTICS
(Ta=25°C; DVDD, AVDD2.7~3.6V, TVDD=2.7~5.5V; CL=20pF)
Parameter
Symbol
min
Master Clock Timing
Crystal Resonator Frequency
fXTAL 11.2896
External Clock
Frequency
Duty
MCKO1 Output
Frequency
Duty
MCKO2 output
Frequency
Duty
PLL Clock Recover Frequency (RX1-4)
LRCK Frequency
Duty Cycle
Audio Interface Timing
Slave Mode
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “”
BICK “” to LRCK Edge
LRCK to SDTO (MSB)
BICK “¯” to SDTO
DAUX Hold Time
DAUX Setup Time
(Note 6)
(Note 6)
Master Mode
BICK Frequency
BICK Duty
BICK “¯” to LRCK
BICK “¯” to SDTO
DAUX Hold Time
DAUX Setup Time
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “¯” to CCLK “”
CCLK "" to CSN “”
CDTO Delay
CSN “” to CDTO Hi-Z
fECLK
dECLK
fMCK1
dMCK1
fMCK2
dMCK2
fpll
fs
dLCK
11.2896
40
5.632
40
2.816
40
22
22
45
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRM
tBSD
tDXH
tDXS
fBCK
dBCK
tMBLR
tBSD
tDXH
tDXS
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
140
60
60
30
30
20
20
-20
20
20
200
80
80
50
50
150
50
50
Reset Timing
PDN Pulse Width
tPW 150
Note 6: BICK rising edge must not occur at the same time as LRCK edge.
typ
50
50
50
-
48
64fs
50
max
24.576
24.576
60
27.648
60
27.648
60
108
108
55
Units
MHz
MHz
%
MHz
%
MHz
%
kHz
kHz
%
ns
ns
ns
ns
ns
35 ns
35 ns
ns
ns
Hz
%
20 ns
40 ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
45 ns
70 ns
ns
MS0020-E-00
-7-
2000/3
7페이지 | |||
구 성 | 총 30 페이지수 | ||
다운로드 | [ AK4112A.PDF 데이터시트 ] |
당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는 |
구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
AK4112A | High Feature 96kHz 24-bit DIR | Asahi Kasei Microsystems |
AK4112B | High Feature 96kHz 24bit DIR | Asahi Kasei Microsystems |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |