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PDF AK4516A Data sheet ( Hoja de datos )
| Número de pieza | AK4516A | |
| Descripción | 3V 16BIT ADC&DAC WITH BUILT-IN PGA | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
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ASAHI KASEI
[AK4516A]
AK4516A
3V 16bit ADC&DAC with built-in PGA
FEATURE
1 . Resolution: 16 bits
2 . Recording Function
• Analog Input PGA (Programmable Gain Amp)
• Peak-Meter Output
• Overflow Flag Output
• Auto Limitter Circuit
• Auto Recovery Circuit
• HPF(fc=3.4Hz) for offset cancel
3 . Playback Function
• Digital De-emphasis Filter(tc=50/15us, fs=32kHz, 44.1kHz, 48kHz)
4 . Analog-Through Mode
5 . Power Management
6 . ADC Input (Including the PGA)
• Single-ended Input
• Input Level: 1.7Vpp (=0.57×VA, VA=3V)
• THD+N: -85dB
• DR,S/N: 90dB
7 . DAC Output
• Single-ended Output
• Output Level: 1.8Vpp (=0.6×VA, VA=3V, RL≥10kΩ)
• Frequency Response: ±0.5dB(∼20kHz)
• THD+N: -86dB
• DR,S/N: 90dB
8 . Master Clock: 256fs/384fs
9 . Audio Data Format
• ADC: 16bit, MSB first,
MSB justified, IIS, LSB justified(only BICK=64fs correspondent)
• DAC: 16bit, MSB first,
MSB justified, IIS, MSB justified
10 . Ta: -20∼85°C
11 . Power Supply: 2.5∼3.6V
12 . Power Dissipation: 18mA
13 . 24pinVSOP (0.65mm Pitch)
M0026-E-00
-1-
1 page  
ASAHI KASEI
ABSOLUTE MAXIMUM RATING
(AGND,DGND=0V; Note 1 )
Parameter
Power Supplies: Analog
Digital
VD-VA
Input Current (Any pin except supplies.)
Analog Input Voltage
LIN1,LIN2,RIN1,RIN2
Digital Input Voltage
Ambient Temperature
Storage Temperature
Note 1 . All Voltage with respect to ground.
Symbol
VA
VD
∆VDA
IIN
VINA
VIND
Ta
Tstg
min
-0.3
-0.3
-
-
-0.3
-0.3
-20
-65
[AK4516A]
max
6.0
6.0
0.3
±10
VA+0.3
VA+0.3
85
150
Units
V
V
V
mA
V
V
°C
°C
RECOMMENDED OPERATING CONDITIONS
(AGND,DGND=0V; Note1 )
Parameter
Power Supplies Analog
Digital
Note 1 . All Voltage with respect to ground
Symbol
VA
VD
min
2.5
2.5
typ
3.0
3.0
max Units
3.6 V
VA V
M0026-E-00
-5-
1998/08
5 Page 
ASAHI KASEI
[AK4516A]
OPERATION OVERVIEW
System Clock
The clocks which are required to operate are MCLK(256fs/384fs), LRCK(fs), BCLK(32fs∼). The master clock
(MCLK) should be synchronized with LRCK but the phase is free of care.
The MCLK can be input 256fs or 384fs. When 384fs is input, the internal master clock is divided into 2/3
automatically. *fs is sampling frequency.
All external clocks (MCLK, BCLK, LRCK) should always be present whenever IPGA or ADC or DAC is in operation.
If these clocks are not provided, the AK4516A may draw excess current and it is not possible to operate properly
because utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4516A should be in
the power-down mode. (Please refer to the "Mode Control 1" section.)
System Reset
AK4516A should be reset once by bringing PD pin "L" upon power-up. The internal timing starts clocking by LRCK
"↑" after exiting reset by MCLK. After the system reset operation, the all internal AK4516A registers are initial value.
Zero detection
When the input data at both channels are continuously zeros for 8192 LRCK cycles, DZF goes to "H". DZF
immediately goes to "L", if the input data are not zero. When the DAC is power-down, DZF becomes to "L".
Digital High Pass Filter(HPF)
The ADC has HPF for the DC offset cancel. The cut-off frequency of HPF is 3.4Hz(@fs=44.1kHz) and it is -0.1dB at
22Hz. It also scales with the sampling frequency(fs).
M0026-E-00
- 11 -
1998/08
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AK4516A.PDF ] | |
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