PDF ADS900E Data sheet ( Hoja de datos )

Número de pieza	ADS900E
Descripción	10-Bit/ 20MHz/ #V Supply ANALOG-TO-DIGITAL CONVERTER
Fabricantes	Burr-Brown Corporation
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No Preview Available ! ® ADS900E ADS900 10-Bit, 20MHz, +3V Supply TM ANALOG-TO-DIGITAL CONVERTER FEATURES q +2.7V TO +3.7V SUPPLY OPERATION q INTERNAL REFERENCE q LOW POWER: 52mW at +3V q SINGLE-ENDED INPUT RANGE: 1V to 2V q WIDEBAND TRACK/HOLD: 350MHz q 28-LEAD SSOP PACKAGE APPLICATIONS q PORTABLE INSTRUMENTATION q IF AND BASEBAND COMMUNICATIONS q CABLE MODEMS q SET-TOP BOXES q PORTABLE TEST EQUIPMENT q COMPUTER SCANNERS ADS900 DESCRIPTION The ADS900 is a high speed pipelined analog-to- digital converter. This complete converter includes a high bandwidth track/hold, a 10-bit quantizer and an internal reference. The ADS900 employs digital error correction tech- niques to provide excellent differential linearity for demanding imaging applications. Its low distortion and high SNR give the extra margin needed for telecommunications, video and test instrumentation applications. This high performance A/D converter is specified for performance at a 20MHz sampling rate. The ADS900 is available in a 28-lead SSOP package. CLK Timing Circuitry LVDD 2V IN 1V IN (Opt.) T/H Pipeline A/D Error Correction 3-State Outputs 10-Bit Digital Data Internal Reference LpBy CM LnBy 1VREF Pwrdn OE International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ©1997 Burr-Brown Corporation PDS-1347B Printed in U.S.A. January, 1997 1 page TYPICAL PERFORMANCE CURVES At TA = +25°C, VS = LVDD = +3V, Single-Ended Input, Sampling Rate = 20MHz, unless otherwise specified. 0 –20 –40 –60 –80 –100 0 SPECTRAL PERFORMANCE fIN = 500kHz 2 4 68 Frequency (MHz) 10 0 –20 –40 –60 –80 –100 0 SPECTRAL PERFORMANCE fIN = 3MHz 2 4 68 Frequency (MHz) 10 0 –20 –40 –60 –80 –100 0 SPECTRAL PERFORMANCE fIN = 9MHz 2 4 68 Frequency (MHz) 10 0 –20 –40 –60 –80 –100 0 TWO-TONE INTERMODULATION f1 = 3.5MHz at –7dBFS f2 = 3.4MHz at –7dBFS 2468 Frequency (MHz) 10 2.0 1.0 0.0 –1.0 –2.0 0 DIFFERENTIAL LINEARITY ERROR fIN = 500kHz 256 512 768 Output Code 1024 2.0 1.0 0.0 –1.0 –2.0 0 DIFFERENTIAL LINEARITY ERROR fIN = 10MHz 256 512 768 Output Code 1024 ® 5 ADS900 5 Page proper op amp should include its output swing, input com- mon-mode range, and bias current. It should be noted that any DC voltage difference between the inputs, IN and IN, will show up as an offset at the output. At the same time an offset adjustment can be accomplished. INTERNAL REFERENCE The ADS900 features an internal pipeline reference that provides fixed reference voltages for the internal stages. As shown in Figure 7 a buffer for each the top and bottom reference is connected to the resistor ladder, which has a nominal resistance of 4kΩ (±15%). The two outputs of the buffers are brought out at pin 21 (LpBy) and pin 25 (LnBy), primarily to connect external bypass capacitors, typically 0.1µF, which will improve the performance. The buffers can drive limited external loads, for example for level shifting of the converter’s interface circuit, however, the current draw should be limited to approximately 1mA. Derived from the top reference of +1.75V is an additional voltage of +1.0V. Note that this voltage, available on pin 23, is not buffered and care should be taken when external loads are applied. In normal operation, this pin is left unconnected and no bypassing components are required. CLOCK INPUT REQUIREMENTS The clock input of the ADS900 is designed to accommodate either +5V or +3V CMOS logic levels. To drive the clock input with a minimum amount of duty cycle variation and support maximum sampling rates (20Msps) high speed or advanced CMOS logic should be used (HC/HCT, AC/ACT). When digitizing at high sampling rates, a 50% duty cycle along with fast rise and fall times (2ns or less) are recom- mended to meet the rated performance specifications. How- ever, the ADS900 performance is tolerant to duty cycle variations of as much as ±10% without degradation. For applications operating with input frequencies up to Nyquist or undersampling applications, special considerations must be made to provide a clock with very low jitter. Clock jitter leads to aperture jitter (tA) which can be the ultimate limita- tion in achieving good SNR performance. Equation (4) shows the relationship between aperture jitter, input fre- quency and the signal-to-noise ratio: SNR = 20log10 [1/(2 π fIN tA)] (4) For example, in the case of a 10MHz full-scale input signal and an aperture jitter of tA = 20ps the SNR is clock jitter limited to 58dB. DIGITAL OUTPUTS The digital outputs of the ADS900 are standard CMOS stages and designed to be compatible to both high speed TTL and CMOS logic families. The logic thresholds are for low-voltage CMOS: VOL = 0.4V, VOH = 2.4V, which allows the ADS900 to directly interface to 3V-logic. The digital outputs of the ADS900 uses a dedicated digital supply pin (pin 2, LVDD) see Figure 8. By adjusting the voltage on LVDD, the digital output levels will vary respectively. It is recommended to limit the fan-out to one to keep the capaci- tive loading on the data lines below the specified 15pF. If necessary, external buffers or latches may be used which provide the added benefit of isolating the A/D converter from any digital activities on the bus coupling back high frequency noise and degrading the performance. CM 0.1µF 26 +1.75V REFT +1.25V REFB ADS900 21 2kΩ 2.1kΩ 23 2.8kΩ 2kΩ 25 LpBy 0.1µF +1VREF LnBy 0.1µF FIGURE 7. Internal Reference Structure and Recommended Reference Bypassing. ® 11 ADS900 11 Page

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