PDF ADV101 Data sheet ( Hoja de datos )

Número de pieza	ADV101
Descripción	CMOS 80 MHz/ Triple 8-Bit Video DAC
Fabricantes	Analog Devices
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No Preview Available ! a CMOS 80 MHz, Triple 8-Bit Video DAC ADV101* FEATURES 80 MHz Pipelined Operation Triple 8-Bit D/A Converters RS-343A/RS-170 Compatible Outputs TTL Compatible Inputs +5 V CMOS Monolithic Construction 40-Pin DIP or 44-Pin PLCC Package Plug-In Replacement for BT101 Power Dissipation: 400 mW APPLICATIONS High Resolution Color Graphics CAE/CAD/CAM Applications Image Processing Instrumentation Video Signal Reconstruction Desktop Publishing SPEED GRADES 80 MHz 50 MHz 30 MHz GENERAL DESCRIPTION The ADV101 is a digital-to-analog video converter on a single monolithic chip. The part is specifically designed for high reso- lution color graphics and video systems. It consists of three, high speed, 8-bit, video D/A converters (RGB); a standard TTL input interface and high impedance, analog output, current sources. The ADV101 has three separate, 8-bit, pixel input ports, one each for red, green and blue video data. Additional video input controls on the part include sync, blank and reference white. A single +5 V supply, an external 1.23 V reference and pixel clock input are all that are required to make the part operational. The ADV101 is capable of generating RGB video output sig- nals, which are compatible with RS-343A and RS-170 video standards, without requiring external buffering. The ADV101 is fabricated in a +5 V CMOS process. Its mono- lithic CMOS construction ensures greater functionality with low power dissipation. The part is packaged in both a 0.6", 40-pin plastic DIP and a 44-pin plastic leaded (J-lead) chip carrier, PLCC. FUNCTIONAL BLOCK DIAGRAM FS VAA ADJUST VREF CLOCK ADV101 REFERENCE AMPLIFIER COMP R0 R7 PIXEL INPUT PORT G0 G7 B0 B7 RED 8 8 REGISTER GREEN 8 8 REGISTER BLUE 8 8 REGISTER DAC DAC DAC IOR IOG IOB REF WHITE BLANK SYNC CONTROL REGISTER SYNC CONTROL ISYNC GND PRODUCT HIGHLIGHTS 1. Fast video refresh rate, 80 MHz. 2. Compatible with a wide variety of high resolution color graphics video systems. 3. Guaranteed monotonic with a maximum differential nonlin- earity of ± 0.5 LSB. Integral nonlinearity is guaranteed to be a maximum of ± 1 LSB. *ADV is a registered trademark of Analog Devices Inc. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 1 page Pin Mnemonic BLANK SYNC CLOCK REF WHITE R0–R7, G0–G7, B0–B7 IOR, IOG, IOB ISYNC FS ADJUST COMP VREF VAA GND PIN FUNCTION DESCRIPTION ADV101 Function Composite blank control input (TTL compatible). A logic zero on this control input drives the analog outputs, IOR, IOB and IOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK. While BLANK is a logical zero, the R0–R7, G0–G7, R0–R7 and REF WHITE pixel and control inputs are ignored. Composite sync control input (TTL compatible). A logical zero on the SYNC input; switches off a 40 IRE cur- rent source on the ISYNC output. SYNC does not override any other control or data input, therefore, it should only be asserted during the blanking interval. SYNC is latched on the rising edge of CLOCK. Clock input (TTL compatible). The rising edge of CLOCK latches the R0–R7, G0–G7, B0–B7, SYNC, BLANK and REF WHITE pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be driven by a dedicated TTL buffer. Reference white control input (TTL compatible). A logical one on this input forces the IOR, IOG and IOB out- puts to the white level, regardless of the pixel input data (R0–R7, G0–G7 and B0–B7) REF WHITE is latched on the rising edge of clock. Red, green and blue pixel data inputs (TTL compatible). Pixel data is latched on the rising edge of CLOCK. R0, G0 and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the regular PCB power or ground plane. Red, green and blue current outputs. These high impedance current sources are capable of directly driving a doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output loads whether or not they are all being used. Sync current output. This high impedance current source can be directly connected to the IOG output. This al- lows sync information to be encoded onto the green channel. ISYNC does not output any current while SYNC is at logical zero. The amount of current output at ISYNC while SYNC is at logical one is given by: ISYNC (mA) = 3,455 × VREF (V)/RSET (Ω) If sync information is not required on the green channel, ISYNC should be connected to AGND. Full-scale adjust control. A resistor (RSET) connected between this pin and GND, controls the magnitude of the full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current. The relationship between RSET and the full-scale output current on IOG (assuming ISYNC is connected to IOG) is given by: RSET (Ω) = 12,082 × VREF (V)/IOG (mA) The relationship between RSET and the full-scale output current on IOR and IOB is given by: IOR, IOB (mA) = 8,628 × VREF (V)/ RSET (Ω) Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF ceramic capacitor must be connected between COMP and VAA. Voltage reference input. An external 1.2 V voltage reference must be connected to this pin. The use of an exter- nal resistor divider network is not recommended. A 0.1 µF decoupling ceramic capacitor should be connected between VREF and VAA. Analog power supply (5 V ± 5%). All VAA pins on the ADV101 must be connected. Ground. All GND pins must be connected. REV. B –5– 5 Page ADV101 Power Planes The PC board layout should have two distinct power planes, one for analog circuitry and one for digital circuitry. The analog power plane should encompass the ADV101 (VAA) and all asso- ciated analog circuitry. This power plane should be connected to the regular PCB power plane (VCC) at a single point through a ferrite bead, as illustrated in Figure 8. This bead should be lo- cated within three inches of the ADV101. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV101 power pins, voltage reference circuitry and any output amplifiers. The PCB power and ground planes should not overlay portions of the analog power plane. Keeping the PCB power and ground planes from overlaying the analog power plane will contribute to a reduction in plane-to-plane noise coupling. Supply Decoupling Noise on the analog power plane can be further reduced by the use of multiple decoupling capacitors. (See Figure 8.) Optimum performance is achieved by the use of 0.1 µF ceramic capacitors. Each of the two groups of VAA should be individually decoupled to ground. This should be done by placing the ca- pacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance. It is important to note that while the ADV101 contains circuitry to reject power supply noise, this rejection decreases with fre- quency. If a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise. A dc power supply filter (Murata BNX002) will provide EMI suppression between the switching power supply and the main PCB. Alternatively, consideration could be given to using a three-terminal voltage regulator. Digital Signal Interconnect The digital signal lines to the ADV101 should be isolated as much as possible from the analog outputs and other analog cir- cuitry. Digital signal lines should not overlay the analog power plane. Due to the high clock rates used, long clock lines to the ADV101 should be avoided so as to minimize noise pickup. Any active pull-up termination resistors for the digital inputs should be connected to the regular PCB power plane (VCC), and not the analog power plane. Analog Signal Interconnect The ADV101 should be located as close as possible to the out- put connectors thus minimizing noise pickup and reflections due to impedance mismatch. The video output signals should overlay the ground plane, and not the analog power plane, thereby maximizing the high fre- quency power supply rejection. For optimum performance, the analog outputs should each have a source termination resistance to ground of 75 Ω (doubly terminated 75 Ω configuration). This termination resistance should be as close as possible to the ADV101 so as to minimize reflections. Additional information on PCB design is available in an applica- tion note entitled “Design and Layout of a Video Graphics Sys- tem for Reduced EMI.” This application note is available from Analog Devices, publication number E1309–15–10/89. REV. B –11– 11 Page

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