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ADM483E 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 ADM483E은 전자 산업 및 응용 분야에서
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부품번호 ADM483E 기능
기능 +-15 kV ESD Protected/ EMC Compliant Slew Rate Limited/ EIA RS-485 Transceiver
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ADM483E 데이터시트, 핀배열, 회로
؎15 kV ESD Protected, EMC Compliant
a Slew Rate Limited, EIA RS-485 Transceiver
ADM483E
FEATURES
Robust RS-485 Transceiver
15 kV ESD Protection Using HBM
2 kV EFT Protection Meets IEC1000-4-4
High EM Immunity Meets IEC1000-4-3
Reduced Slew Rate for Low EM Interference
250 kbps Data Rate
Single +5 V ؎ 10% Supply
–7 V to +12 V Bus Common-Mode Range
12 kInput Impedance
Short Circuit Protection
Excellent Noise Immunity
36 A Supply Current
0.1 A Shutdown Current
APPLICATIONS
Low Power RS-485 Systems
Electrically Harsh Environments
EMI Sensitive Applications
DTE-DCE Interface
Packet Switching
Local Area Networks
FUNCTIONAL BLOCK DIAGRAM
ADM483E
RO R
RE
DE
DI D
B
A
GENERAL DESCRIPTION
The ADM483E is a robust, low power differential line trans-
ceiver suitable for communication on multipoint bus transmis-
sion lines. Internal protection against electrostatic discharge
(ESD), electrical fast transient (EFT) and electromagnetic
immunity (EMI) allows operation in electrically harsh environ-
ments. ESD protection on the I-O lines meets ± 15 kV when
tested using the Human Body Model. EFT protection meets
± 2 kV in accordance with IEC1000-4-4, while EMI immunity is
in excess of 10 V/m meeting IEC1000-4-3.
The level of unwanted emissions is also carefully controlled
using slew limiting on the driver outputs. This reduces reflec-
tions with improperly terminated cables and also minimizes
electromagnetic interference. The controlled slew rate limits the
data rate to 250 kbps.
The ADM483E is intended for balanced data transmission and
complies with both EIA Standards RS-485 and RS-422. It
contains a differential line driver and a differential line receiver
and is suitable for half duplex data transmission, as the driver
and receiver share the same differential pins.
The input impedance on the ADM483E is 12 k, allowing up
to 32 transceivers on the bus.
The ADM483E operates from a single +5 V ± 10% power sup-
ply. Excessive power dissipation caused by bus contention or by
output shorting is prevented by a thermal shutdown circuit. This
feature forces the driver output into a high impedance state if,
during fault conditions, a significant temperature increase is
detected in the internal driver circuitry.
The receiver contains a fail-safe feature that results in a logic
high output state if the inputs are unconnected (floating).
The ADM483E is fabricated on BiCMOS, an advanced mixed
technology process combining low power CMOS with robust
bipolar technology.
It is fully specified over the industrial temperature range and is
available in 8-lead DIP and SOIC packages.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997




ADM483E pdf, 반도체, 판매, 대치품
ADM483E
Test Circuits
VOD
R
R VOC
Figure 1. Driver Voltage Measurement Test Circuit
VOD3
375
60
375
VTST
Figure 2. Driver Voltage Measurement Test Circuit 2
0V OR 3V
DE IN
A
DE B
S1
RL
CL
VOUT
VCC
S2
Figure 3. Driver Enable/Disable Test Circuit
+15V
S1
–15V
RE IN
RE
RL
CL
VOUT
VCC
S2
Figure 4. Receiver Enable/Disable Test Circuit
DI
D
RLDIFF
CL1
CL2
A
RO
R
B
RE
Figure 5. Receiver Propagation Delay Test Circuit
Switching Characteristics
3V
1.5V
0V TPLH
B
VO
A
1/2VO
VO
0V
–VO
90% POINT
10% POINT
TR
TSKEW
1.5V
TPHL
TSKEW
90% POINT
10% POINT
TF
Figure 6. Driver Propagation Delay, Rise/Fall Timing
A–B
RO
0V
TPLH
1.5V
0V
TPHL
1.5V
VOH
VOL
Figure 8. Receiver Propagation Delay
–4–
DE 1.5V
TZL
1.5V
TLZ
3V
0V
A, B
A, B
2.3V
TZH
2.3V
VOL+ 0.5V
VOL
THZ
VOH
VOH – 0.5V
0V
Figure 7. Driver Enable/Disable Timing
RE 1.5V
TZL
1.5V
TLZ
3V
0V
R 1.5V
O/P LOW
VOL+ 0.5V
VOL
TZH THZ
O/P HIGH
VOH
R 1.5V
VOH – 0.5V
0V
Figure 9. Receiver Enable/Disable Timing
REV. 0

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ADM483E 전자부품, 판매, 대치품
ADM483E
I-O lines are particularly vulnerable to ESD damage. Simply
touching or plugging in an I-O cable can result in a static
discharge that can damage or completely destroy the interface
product connected to the I-O port.
It is, therefore, extremely important to have high levels of ESD
protection on the I-O lines.
It is possible that the ESD discharge could induce latchup in the
device under test. It is therefore important that ESD testing on
the I-O pins be carried out while device power is applied. This
type of testing is more representative of a real world I-O
discharge where the equipment is operating normally when the
discharge occurs.
100%
90%
V
300ms
V
5ns
16ms
t
0.2/0.4ms
50ns
t
Figure 23. IEC1000-4-4 Fast Transient Waveform
Table V shows the peak voltages for each of the environments.
Table V.
36.8%
10%
tRL
tDL
TIME t
Figure 22. Human Body Model ESD Current Waveform
Table IV. ADM483E ESD Test Results
ESD Test Method
I-O Pins
Other Pins
Human Body Model: Air
Human Body Model: Contact
± 15 kV
± 8 kV
± 3.5 V
FAST TRANSIENT BURST IMMUNITY (IEC1000-4-4)
IEC1000-4-4 (previously 801-4) covers electrical fast-transient/
burst (EFT) immunity. Electrical fast transients occur as a
result of arcing contacts in switches and relays. The tests
simulate the interference generated when, for example, a power
relay disconnects an inductive load. A spark is generated due to
the well known back EMF effect. In fact, the spark consists of a
burst of sparks as the relay contacts separate. The voltage
appearing on the line, therefore, consists of a burst of extremely
fast transient impulses. A similar effect occurs when switching
on fluorescent lights.
The fast transient burst test, defined in IEC1000-4-4, simulates
this arcing and its waveform is illustrated in Figure 23. It
consists of a burst of 2.5 kHz to 5 kHz transients repeating at
300 ms intervals. It is specified for both power and data lines.
Four severity levels are defined in terms of an open-circuit
voltage as a function of installation environment. The installa-
tion environments are defined as
1. Well-protected
2. Protected
3. Typical Industrial
4. Severe Industrial
Level
1
2
3
4
VPEAK (kV)
PSU
0.5
1
2
4
VPEAK (kV)
I-O
0.25
0.5
1
2
A simplified circuit diagram of the actual EFT generator is
illustrated in Figure 24.
These transients are coupled onto the signal lines using an EFT
coupling clamp. The clamp is 1 m long and completely sur-
rounds the cable, providing maximum coupling capacitance
(50 pF to 200 pF typ) between the clamp and the cable. High
energy transients are capacitively coupled onto the signal lines.
Fast rise times (5 ns) as specified by the standard result in very
effective coupling. This test is very severe since high voltages are
coupled onto the signal lines. The repetitive transients can often
cause problems, where single pulses do not. Destructive latchup
may be induced due to the high energy content of the transients.
Note that this stress is applied while the interface products are
powered up and are transmitting data. The EFT test applies
hundreds of pulses with higher energy than ESD. Worst case
transient current on an I-O line can be as high as 40 A.
HIGH
VOLTAGE
SOURCE
RC
CC
L RM CD
ZS
50
OUTPUT
Figure 24. EFT Generator
Test results are classified according to the following
1. Normal performance within specification limits.
2. Temporary degradation or loss of performance that is self-
recoverable.
3. Temporary degradation or loss of function or performance
that requires operator intervention or system reset.
4. Degradation or loss of function that is not recoverable due to
damage.
REV. 0
–7–

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