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ADM8840 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 ADM8840은 전자 산업 및 응용 분야에서
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부품번호 ADM8840 기능
기능 Charge Pump Regulator & COM Driver for Color TFT Panel
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로고 Analog Devices 로고


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ADM8840 데이터시트, 핀배열, 회로
PRELIMINARY TECHNICAL DATA
a
Charge Pump Regulator & COM Driver
for Color TFT Panel
Preliminary Technical Data
ADM8840
FEATURES
Programmable COM Driver to prevent Screen-Burn
3 Voltages (5.0V,15.0V,-15.0V) from one 3V Supply
Power Efficiency optimised for use with TFT in mobile
phones
Low Quiescent Current
Low Shutdown Current (<5uA)
Shutdown Function
APPLICATIONS
Handheld Instruments
TFT LCD Panels
Cellular Phones
SHDN
C6
4.7F
VCC
DAC1_IN
D AC 1 _S D
FUNCTIONAL BLOCK DIAGRAM
ADM8840
OS CI L L AT O R
TIMING
G E N E R A T OR
S H UT D OW N
C ON T RO L
DI S C HARG E
CONTROL
LOGIC
VOLTAGE
IN VE RT ER
TRIP LE
VOLTAGE
TRIPLER
DOUBLE
LDO
VOLTAGE
RE G UL ATO R
V OL T AG E
DOUBLER
V O LT AGE
ADDER
C4+
C4
0.22F
C4-
C2+
C2
0.22F
C2-
C3+
C3
0. 2 2F
C3-
-15V
C9 0.22F
+15V
C8 0.22F
5VIN
5V O UT
+5V
C7 2.2F
C1+
C1
3.3F
C 1-
VOUT
C10
3.3F
C5+
C5
3.3F
C5-
GENERAL DESCRIPTION
The ADM8840 combines a charge pump regulator and a
Common Line (COM) driver in a single chip solution for use
in TFT LCD’s. The device provides an LCD controller and
grayscale DAC supply voltage of 5.0V (±2%), 2 gate drive
voltages of +15V and -15V and a COM driver voltage. This
COM Driver voltage alternates the polarity of the Common
line voltage every line (or every frame) on the display in order
to prevent screen-burn occuring over time. The ADM8840
is powered by a single 3.0V supply.
The ADM8840 has an internal 100KHz oscillator for driving
the charge pumps.
The COM Driver section of the ADM8840 can be used to
generate the alternate frame or line inversion of the COM
line of the LCD panel. The ADM8840 receives the COM
clock from the controller with a frequency up to 10kHz and
allows programmable conditioning of its amplitude and
centre voltage through the use of on-board DAC’s. This
allows programmable elimination of display flicker caused
by the COM inversion.
The COM_OUT amplitude can be programmed from 4.0V
to 7.0V in steps of 28mV. The COM_OUT centre voltage
can be programmed to 0.9V to 2.8V in steps of 14mV.
VREF
CLK
D ATA
CS / LDAC
8
SERIAL
INTERFACE
8
DAC 1
DAC 2
CO M _I N
DAC2_SD
D AC 2_I N
IN T /E XT
DAC 1
INT/EXT
DAC 2
ADD _ OUT
C11
+ 4.7F
-
LEVEL
TRANSLATOR
POWER
BUFFER
T R AN S_ O UT
C12
4.7F
C OM _ OU T _AC
C13
4.7F
+ COM_OUT
- 5.5k
CPANEL
22nF
GND
The ADM8840 provides power up sequencing of the -15V
and +15V gate drive outputs, ensuring the -15V starts to
power up before the +15V.
The ADM8840 has a number of power save features, includ-
ing low power Shutdown. The 5.0V output consumes the
most power, so Power Efficiency is also maximised on this
output with an oscillator enabling scheme (Green IdleTM).
The ADM8840 is fabricated using CMOS technology for
minimal power consumption. The part is packaged in a 32-
pin LFCSP package.
TM Green Idle is a registered trademark of Analog Devices Inc.
REV. PrG 2/03
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
Analog Devices, Inc., 2003




ADM8840 pdf, 반도체, 판매, 대치품
PRELIMINARY TECHNICAL DATA
ADM8840
Timing Specifications
VCC = +3V-10%,+20%, TA=-40°C to +85°C
PARAMETER
POWER-UP SEQUENCE
5V Rise time, TR5V
+15V Rise time, TR15V
-15V Fall time, TF15V
Delay between VCC rise
and SHDN rise, TDELAY1
Delay between -15V fall
and +15V rise, TDELAY2
Min
Typ
TBD
TBD
TBD
TBD
TBD
Max
Units
Test Conditions /Comments
us 10% to 90%, Figure 2
ms 10% to 90%, Figure 2
ms 90% to 10%, Figure 2
ms Figure 2
ms Figure 2
POWER- DOWN SEQUENCE
5V Fall time, TF5V
+15V Fall time, TF15V
-15V Rise time, TR15V
TBD
TBD
TBD
ms 90% to 10%, Figure 2
ms 90% to 10%, Figure 2
ms 10% to 90%, Figure 2
SERIAL INTERFACE
t1
t2
t3
t4
t5
t6
t7
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ns CS/LDAC falling edge to SCLK
Rising Edge; Note 1; Note2
ns SCLK High Pulsewidth; Note 1; Note2
ns SCLK Low Pulsewidth; Note 1; Note2
ns Minumum CS/LDAC high time;
Note 1; Note2
ns SCLK Rising Edge to CS/LDAC
Rising Edge; Note 1; Note2
ns DATA Setup time; Note 1; Note2
ns DATA Hold time; Note 1; Note2
NOTES
1. Guaranteed by Design. Not 100% Production Tested.
2. See Timing Diagram in Figure 4.
* Specifications are target values and are subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(TA=25oC unless otherwise noted.)
Supply Voltage
-0.3 V to +4.0 V
Model
ORDERING GUIDE
Temperature
Range
Package
Option
Input Voltage on Digital Inputs
Output Short Circuit Duration to GND
Output Voltage
+5.0V Output
-15.0V Output
+15.0V Output
Operating Temperature Range
Power Dissipation
Storage Temperature Range
ESD
-0.3 V to +4.0 V
10 seconds
-0.3 V to +6.0 V
-17 V to +0.3 V
-0.3 V to +17 V
-40°C to +85°C
50mW
-65°C to +150°C
Class I
ADM8840ACP -40°C to +85°C CP-32
PIN CONFIGURATION
C1+ 1
32 31 30 29 28 27 26 25
ADM8840
TOP VIEW
24 C3-
*Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above
those indicated in the operational section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
VCC 2
VOUT 3
5VOUT 4
5VIN 5
SHDN 6
(NOT TO SCALE)
23 15VOUT
22 VCC
21 C5-
20 C5+
19 ADD_OUT
DAC1_SD 7
18 COM_IN
THERMAL CHARACTERISTICS
32-Lead LFCSP Package:
JA = 28°C/Watt
DAC2_SD 8
17 GND
9 10 11 12 13 14 15 16
–4– REV. PrG 2/03

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ADM8840 전자부품, 판매, 대치품
PRELIMINARY TECHNICAL DATA
SERIAL INTERFACE
The COM Driver section of the ADM8840 uses a serial
interface to input data and transfer it into the DACs. Figure
3, below, shows the operation of the serial interface. The data
is transmitted along the serial DATA line, along with a serial
clock signal, SCLK. This data is read into a Shift Register.
When the 8 bits are sucessfully stored in the Shift Register a
low-to-high transition on the CS/LDAC input causes the
latch to load the 8-bits of data into the relevent DAC.
This function is also shown in the waveforms in Figure 4
below. A falling edge on the CS/LDAC input initiates the
data read into the shift register. The first bit of the datastream
is the DAC Select Bit (DAC_SEL) which determines which
internal DAC the data will be written to. A ‘1’ selects DAC
1 which sets the Amplitude of the output and a ‘0’ selects
ADM8840
DAC 2 which sets the Centre Voltage of the output. The
individual data bits are then read in one by one on the DATA
line. After the DAC_SEL bit and the 8 data bits have been
read there is a pause to ensure the shift register outputs are
stable. Then a rising edge on the CS/LDAC input loads the
8 bits on the shift register outputs into the relevent DAC (and
the DAC outputs will change accordingly). Note that if CS/
LDAC goes high before all 8 data bits are read in then
incorrect data will be loaded into the DACs. All bits on the
DATA line are read in on each rising edge of the SCLK
signal.
When the ADM8840 comes out of shutdown the DACs
are preset with default values generating a COM_OUT
Amplitude of 6V with a Centre voltage of 1.5V.
DATA
SHIFT
REGISTER
8 DATA BITS
DAC 1
LATCH
SCLK
DAC_SEL BIT
DAC
SELECT
DAC 2
LATCH
DAC 1
(AMPLITUDE)
DAC 1 OUT
DAC 2
(CENTRE VOLTAGE)
DAC 2 OUT
CS/LDAC
Figure 3. Serial Interface Diagram
CS / LDAC
t1
t3
t2
t4
SCLK
DATA
D AC
SEL
D0
D1 D2
D3 D4
D5 D6 D7
REV. PrG 2/03
t7
t6
Figure 4. Serial Interface Waveforms
7
t5

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