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PDF ADM8840ACP Data sheet ( Hoja de datos )
| Número de pieza | ADM8840ACP | |
| Descripción | Charge Pump Regulator & COM Driver for Color TFT Panel | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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PRELIMINARY TECHNICAL DATA
a
Charge Pump Regulator & COM Driver
for Color TFT Panel
Preliminary Technical Data
ADM8840
FEATURES
Programmable COM Driver to prevent Screen-Burn
3 Voltages (5.0V,15.0V,-15.0V) from one 3V Supply
Power Efficiency optimised for use with TFT in mobile
phones
Low Quiescent Current
Low Shutdown Current (<5uA)
Shutdown Function
APPLICATIONS
Handheld Instruments
TFT LCD Panels
Cellular Phones
SHDN
C6
4.7 F
VCC
DAC1_IN
D AC 1 _S D
FUNCTIONAL BLOCK DIAGRAM
ADM8840
OS CI L L AT O R
TIMING
G E N E R A T OR
S H UT D OW N
C ON T RO L
DI S C HARG E
CONTROL
LOGIC
VOLTAGE
IN VE RT ER
TRIP LE
VOLTAGE
TRIPLER
DOUBLE
LDO
VOLTAGE
RE G UL ATO R
V OL T AG E
DOUBLER
V O LT AGE
ADDER
C4+
C4
0.22F
C4-
C2+
C2
0.22F
C2-
C3+
C3
0. 2 2 F
C3-
-15V
C9 0.22F
+15V
C8 0.22F
5VIN
5V O UT
+5V
C7 2.2F
C1+
C1
3.3F
C 1-
VOUT
C10
3.3F
C5+
C5
3.3F
C5-
GENERAL DESCRIPTION
The ADM8840 combines a charge pump regulator and a
Common Line (COM) driver in a single chip solution for use
in TFT LCD’s. The device provides an LCD controller and
grayscale DAC supply voltage of 5.0V (±2%), 2 gate drive
voltages of +15V and -15V and a COM driver voltage. This
COM Driver voltage alternates the polarity of the Common
line voltage every line (or every frame) on the display in order
to prevent screen-burn occuring over time. The ADM8840
is powered by a single 3.0V supply.
The ADM8840 has an internal 100KHz oscillator for driving
the charge pumps.
The COM Driver section of the ADM8840 can be used to
generate the alternate frame or line inversion of the COM
line of the LCD panel. The ADM8840 receives the COM
clock from the controller with a frequency up to 10kHz and
allows programmable conditioning of its amplitude and
centre voltage through the use of on-board DAC’s. This
allows programmable elimination of display flicker caused
by the COM inversion.
The COM_OUT amplitude can be programmed from 4.0V
to 7.0V in steps of 28mV. The COM_OUT centre voltage
can be programmed to 0.9V to 2.8V in steps of 14mV.
VREF
CLK
D ATA
CS / LDAC
8
SERIAL
INTERFACE
8
DAC 1
DAC 2
CO M _I N
DAC2_SD
D AC 2_I N
IN T /E XT
DAC 1
INT/EXT
DAC 2
ADD _ OUT
C11
+ 4.7F
-
LEVEL
TRANSLATOR
POWER
BUFFER
T R AN S_ O UT
C12
4.7F
C OM _ OU T _AC
C13
4.7F
+ COM_OUT
- 5.5k⍀
CPANEL
22nF
GND
The ADM8840 provides power up sequencing of the -15V
and +15V gate drive outputs, ensuring the -15V starts to
power up before the +15V.
The ADM8840 has a number of power save features, includ-
ing low power Shutdown. The 5.0V output consumes the
most power, so Power Efficiency is also maximised on this
output with an oscillator enabling scheme (Green IdleTM).
The ADM8840 is fabricated using CMOS technology for
minimal power consumption. The part is packaged in a 32-
pin LFCSP package.
TM Green Idle is a registered trademark of Analog Devices Inc.
REV. PrG 2/03
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
Analog Devices, Inc., 2003
1 page  
Pin
1,32
2, 22
3
4
5
6
7
9
17, 31
13
12
11
18
16
14
8
10
15
PRELIMINARY TECHNICAL DATA
Mnemonic
PIN FUNCTION DESCRIPTION
Function
ADM8840
C1+,C1-
VCC
VOUT
+5VOUT
+5VIN
SHDN
DAC1_SD
DAC1_IN
GND
SCLK
DATA
CS / LDAC
COM_IN
COM_OUT_AC
COM_OUT
DAC2_SD
DAC2_IN
TRANS_OUT
External capacitor C1 is connected between these pins. A 3.3F capacitor is
recommended.
Positive Supply Voltage Input. Connect this pin to 3V supply. A 4.7F
decoupling capacitor should be attached close to pin 2.
Voltage Doubler Output. This was derived by doubling the 3V supply. A 3.3F
capacitor to ground is required on this pin.
+5.0V output pin. This was derived by doubling and regulating the +3V supply.
A 2.2F capcitor to ground is required on this pin to stabilise the regulator.
+5.0V input pin. This is the input to the voltage tripler and inverter charge pump
circuits.
Digital Input. 3V CMOS Logic. Active low shutdown control. This shuts down
the timing generator and enables the discharge circuit to dissipate the charge on
the voltage outputs, thus driving them to 0V.
Switches over to external DAC1 input when asserted.
Input for external DAC1 signal.
Device Ground Pin.
External Clock Input. Used to load DAC 1 with COM Voltage amplitude and
DAC 2 with COM Centre Voltage.
Digital Data Input to both DAC’s 1 and 2.
Dual function pin.
1.Chip Select. Digital Input Logic. Chip Select for Digital Interface.
2. Load DAC. Digital Input Logic. DAC’s 1 and 2 perform a conversion on a
low-to-high transition.
Clock Input from digital controller chip. This input is level shifted, offset and
inverted to provide a COM Voltage output swing at a frequency of the COM_IN
input.
COM_OUT_AC outputs the COM_IN signal inverted and level shifted by the
value programmed on DAC 1. A 4.7F capacitor is connected between this pin
and COM_OUT.
The AC output on COM_OUT_AC is added to the center voltage programmed on
DAC2 so that the desired amplitude, centered about the correct center voltage
appears on COM_OUT. The load capacitance seen by this pin is the bulk capaci
tance of the panel, typically 20nF.
Switches over to external DAC2 input when asserted.
Input for external DAC2 signal.
Level Translator Reference Output Voltage. This is the voltage that the value on
DAC 1 is gained up to to provide the upper voltage for the Level Translator. A
voltage of between 4.0V and 7.0V can be output here. A 4.7F cap is
recommended for this pin.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADM8840 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. PrG 2/03
–5–
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet ADM8840ACP.PDF ] | |
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