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부품번호 ADMC201 기능
기능 Motion Coprocessor
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ADMC201 데이터시트, 핀배열, 회로
a
Motion Coprocessor
ADMC201
FEATURES
Analog Input Block
11-Bit Resolution Analog-to-Digital (A/D) Converter
7 Single-Ended (SE) Analog Inputs
4 Simultaneously Sampled Analog Inputs
Expansion with 4 Multiplexed Inputs
3.2 s Conversion Time/Channel
0 V–5 V Analog Input Range
Internal 2.5 V Reference
PWM Synchronized Sampling Capability
12-Bit PWM Timer Block
Three-Phase Center-Based PWM
1.5 kHz–25 kHz PWM Switching Frequency Range
Programmable Deadtime
Programmable Pulse Deletion
PWM Synchronized Output
External PWM Shutdown
Vector Transformation Block
12-Bit Vector Transformations
Forward and Reverse Clarke Transformations
Forward and Reverse Park Rotations
2.9 s Transformation Time
Programmable Digital I/O Port
6-Bit Configurable Digital I/O
Change of State Interrupt Support
DSP & Microcontroller Interface
12 Bit Memory Mapped Registers
Twos Complement Data Format
6.25 MHz to 25 MHz Operating Clock Range
68-Pin PLCC Package
Single 5 V DC Power Supply
Industrial Temperature Range
GENERAL DESCRIPTION
The ADMC201 is a motion coprocessor that can be used with
either microcontrollers or digital signal processors (DSP). It
provides the functionality that is required to implement a digital
control system. In a typical application, the DSP or micro-
controller performs the control algorithms (position, speed,
torque and flux loops) and the ADMC201 provides the neces-
sary motor control functions: analog current data acquisition,
vector transformation, digital inputs/outputs, and PWM drive
signals.
PRODUCT HIGHLIGHTS
Simultaneous Sampling of Four Inputs
A four channel sample and hold amplifier allows three-phase
motor currents to be sampled simultaneously, reducing errors
from phase coherency. Sample and hold acquisition time is
1.6 µs and conversion time per channel is 3.2 µs (using a 12.5 MHz
system clock).
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
RESET
WR
A0–3
RD
CS
IRQ
CLK
REFOUT
REFIN
CONVST
U
V
W
AUX
AUX0
AUX1
AUX2
AUX3
PWMSYNC
A
AP
B
BP
C
CP
STOP
FUNCTIONAL BLOCK DIAGRAM
D0–D11
DATABUS
EMBEDDED
CONTROL
SEQUENCER
CONTROL BUS
INTERNAL
REFERENCE
CONTROL
REGISTERS
11-BIT
A/D
CONVERTER
MULTIPLEXER
EXPANSION
BLOCK
12-BIT
PWM TIMER
BLOCK
VECTOR
TRANSFORMATION
BLOCK
PROG.
DIGITAL
I/O
PORT
PIO 0–5
Flexible Analog Channel Sequencing
The ADMC201 supports acquisition of 2, 3, or 4 channels per
group. Converted channel results are stored in registers and
the data can be read in any order. The sampling and conversion
time for two channels is 8 µs, three channels is 11.2 µs, and four
channels is 14.4 µs (using a 12.5 MHz system clock).
Embedded Control Sequencer
The embedded control sequencer off-loads the DSP or micro-
processor, reducing the instructions required to read analog
input channels, control PWM timers and perform vector trans-
formations. This frees the host processor for performing control
algorithms.
Fast DSP/Microprocessor Interface
The high speed digital interface allows direct connection to 16-bit
digital signal processors and microprocessors. The ADMC201
has 12 bit memory mapped registers with twos complement
data format and can be mapped directly into the data memory
map of a DSP. This allows for a single instruction read and write
interface.
Integration
The ADMC201 integrates a four channel simultaneous sampling
analog-to-digital converter, four channel analog multiplexer,
analog reference, vector transformation, six digital inputs/outputs,
and three-phase PWM timers into a 68-pin PLCC. Integration
reduces cost, board space, power consumption, and design and
test time.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000




ADMC201 pdf, 반도체, 판매, 대치품
ADMC201
CLK
CS
A0A3
RD
DATA
23 22
20 21
26
25
16
18
19
17
Figure 4. Read Cycle Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V
Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD
Analog Reference Input Voltage . . . . . . . . . . . . –0.3 V to VDD
Digital Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD
Analog Reference Output Swing . . . . . . . . . . . . –0.3 V to VDD
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +280°C
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at
these or any other conditions greater than those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Part
Number
ADMC201AP
Temperature
Range
–40°C to +85°C
Package
Description
68-Pin PLCC
Package
Option
P-68A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADMC201 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
4REV. B

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ADMC201 전자부품, 판매, 대치품
ADMC201
PWM TIMER BLOCK OVERVIEW
The PWM timers have 12-bit resolution and support program-
mable pulse deletion and deadtime. The ADMC201 generates
three center-based signals A, B and C based upon user-supplied
duty cycles values. The three signals are then complemented
and adjusted for programmable deadtime to produce the six
outputs. The ADMC201 PWM master switching frequency can
range from 2.5 kHz to 20 kHz, when using a 10 MHz system
clock. The master frequency selection is set as a fraction of the
PWMTM register. If the system clock is 10 MHz, then the
minimum edge resolution available is 100 ns.
The output format of the PWM block is active LO. There is an
external input to the PWM timers (STOP) that will disable all
six outputs within one system clock when the input is HIGH.
The ADMC201 has a PWM Synchronization output
(PWMSYNC) which brings out the master switching frequency
from the PWM timers. The width of the PWMSYNC pulse is
equal to one system clock cycle. For example, if the system clock
is 10 MHz, the PWMSYNC width would be equal to 100 ns.
PWM Master Switching Period Selection
The switching time is set by the PWMTM register which should
be loaded with a value equal to the system clock frequency
divided by the desired master switching frequency. For ex-
ample, if the desired switching frequency is 8 kHz and the
system clock frequency is 10 MHz, then the PWMTM register
should be loaded with 1250 (10 MHz/8 kHz). The PWMCHA,
PWMCHB and PWMCHC registers are loaded with the
desired on-time and their values would be calculated as a ratio
of the PWMTM register value. Note: Desired Pulse Density =
(PWMCHx register)/( PWMTM register).
The beginning of each PWM cycle is marked by the PWMSYNC
signal. New values of PWMCHA, PWMCHB and PWMCHC
must all be loaded into their respective registers at least four sys-
tem clock cycles before the beginning of a new PWM cycle. All
three registers must be updated for any of them to take effect.
New PWM on/off times are calculated during these four clock
cycles and therefore the PWMCHA, PWMCHB and PWMCHC
registers must be loaded before this time. If this timing require-
ment is not met, then the PWM outputs may be invalid during
the next PWM cycle.
PWM Example
The following example uses a system clock speed of 10 MHz.
The desired PWM master switching frequency is 8 kHz and the
desired on-time for the timers A, B and C are 25%, 50% and
10% respectively. The values for the PWMCHA, PWMCHB
and PWMCHC registers must be calculated as ratios of the
PWMTM register (1250 in this example). To achieve these
duty cycles, load the PWMCHA register with 313 (1250 ×
0.25), PWMCHB with 625 (1250 × 0.5) and PWMCHC with
125 (1250 × 0.1).
Programmable Deadtime
With perfectly complemented PWM drive signals and nonideal
switching characteristics of the power devices, both transistors
in a particular leg might be switched on at the same time, result-
ing in either a power supply trip, inverter trip or device
destruction. In order to prevent this, a delay must be intro-
duced between the complemented signal edges. For example,
the rising edge of AP occurs before the falling edge of A, and the
falling edge of the complemented A occurs after the rising edge
of A. This capability is known as programmable deadtime.
The ADMC201 programmable deadtime value is loaded into
the 7-bit PWMDT register, in which the LSB is set to zero in-
ternally, which means the deadtime value is always divisible by
two. With a 10 MHz system clock, the 0126 range of values in
PWMDT yield a range of deadtime values from 0 µs to 12.6 µs
in 200 ns steps. Figure 6 shows PWM timer A with a program-
mable deadtime of PWMDT.
PWMTM
PWMCHA - PWMDT
A
AP
PWMCHA + PWMDT
Figure 6. Programmable Deadtime Example
Pulse Deletion
The pulse deletion feature prevents a pulse from being gener-
ated when the user-specified duty cycle results in a pulse
duration shorter than the user-specified deletion value. The
pulse deletion value is loaded into the 7-bit register PWMPD.
When the user-specified on-time for a channel would result in a
calculated pulse width less than the value specified in the
PWMPD register, then the PWM outputs for that channel
would be set to full off (0%) and its prime to full on (100%).
This is valid for A, AP, B, BP, C and CP. This feature would
be used in an environment where the inverters power transis-
tors have a minimum switching time. If the user-specified duty
cycle would result in a pulse duration shorter than the minimum
switching time of the transistors, then pulse deletion should be
used to prevent this occurrence. With a 10 MHz system clock,
the 0127 range of values in PWMPD yield a range of deadtime
values from 0 µs to 12.7 µs in 100 ns steps.
External PWM Shutdown
There is an external input pin (STOP) to the PWM timers that
will disable all six outputs when it goes HIGH. When the STOP
pin goes HIGH, the PWM timer outputs will all go HIGH
within one system clock cycle. When the STOP pin goes LOW,
the PWM timer outputs are re-enabled within one system clock
cycle. If external PWM shutdown isn't required, tie the STOP
pin LOW.
REV. B
7

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