PDF ADMC300-PB Data sheet ( Hoja de datos )

Número de pieza	ADMC300-PB
Descripción	High Performance DSP-Based Motor Controller
Fabricantes	Analog Devices
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No Preview Available ! a High Performance DSP-Based Motor Controller ADMC300 TARGET APPLICATIONS Industrial Drives, Servo Drives, Variable Speed Drives, Electric Vehicles FEATURES 25 MIPS Fixed-Point DSP Core Single Cycle Instruction Execution (40 ns) ADSP-2100 Family Code Compatible Independent Computational Units ALU Multiplier/Accumulator Barrel Shifter Multifunction Instructions Single Cycle Context Switch Powerful Program Sequencer Zero Overhead Looping Conditional Instruction Execution Two Independent Data Address Generators Memory Configuration 4K ؋ 24-Bit Program Memory RAM 2K ؋ 24-Bit Program Memory ROM 1K ؋ 16-Bit Data Memory RAM High-Resolution Multichannel ADC System Five Independent 16-Bit Sigma-Delta ADCs 76 dB SNR Typical (ENOB > 12 Bits) Arranged in Two Independently Clocked Banks Differential or Single-Ended Inputs Programmable Sample Frequency to 32.5 kHz Flexible Synchronization of ADC and PWM Subsystems Independent Offset Calibration for Each Channel Two Dedicated ADC Interrupts Internal 2.5 V Reference Three Multiplexer Control Pins for External Expansion Hardware or Software Convert Start Individual Power-Down for Each Bank Three-Phase PWM Generation Subsystem 16-Bit Dedicated PWM Generator Edge Resolution to 40 ns Programmable Dead Time Programmable Minimum Pulsewidth Double Update Mode Allows Duty Cycle Adjustment on Half Cycle Boundaries Special Features for Brushless DC Motors Hardwired Polarity Control External Dedicated Asynchronous Shutdown Pin (PWMTRIP) Additional Shutdown Pins in I/O System Individual Enable/Disable of Each Output High Frequency Chopping Mode Transparent Transition to Overmodulation Range with Duty Cycles of 100% Programmable Interrupt Controller Manages Priority and Masking of 11 Peripheral Interrupts (Continued on Page 7) FUNCTIONAL BLOCK DIAGRAM ADSP-2100 BASE ARCHITECTURE DATA ADDRESS GENERATORS DAG 1 DAG 2 PROGRAM SEQUENCER PROGRAM ROM 2K ؋ 24 PROGRAM RAM 4K ؋ 24 MEMORY DATA RAM 1K ؋ 16 MOTOR CONTROL PERIPHERALS 3 2 12 WATCH- DOG TIMER PROGRAM INTERRUPT CONTROLLER ENCODER INTERFACE EVENT CAPTURE TIMERS DIGITAL I/O PROGRAM MEMORY ADDRESS BUS DATA MEMORY ADDRESS BUS PROGRAM MEMORY DATA BUS DATA MEMORY DATA BUS ARITHMETIC UNITS ALU MAC SHIFTER SERIAL PORTS SPORT 0 SPORT 1 56 INTERVAL TIMER REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. AUXILIARY PWM SIGMA-DELTA ADCs PWM GENERATION 2 10 7 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 1 page Parameter Serial Ports Timing Requirements: tSCK SCLK Period tSCS DR/TFS/RFS Setup before SCLK Low tSCH DR/TFS/RFS Hold after SCLK Low tSCP SCLKIN Width Switching Characteristics: tCC tSCDE tSCDV tRH tRD tSCDH tSCDD CLKOUT High to SCLKOUT SCLK High to DT Enable SCLK High to DT Valid TFS/RFSOUT Hold after SCLK High TFS/RFSOUT Delay from SCLK High DT Hold after SCLK High SCLK High to DT Disable Specifications subject to change without notice. Min 50 5 10 20 0.25 tCK 0 0 0 CLKOUT SCLK DR RFSIN TFSIN RFSOUT TFSOUT DT tCC tRD tRH tSCDV tSCDE tCC tSCS tSCH tSCP tSCK tSCP tSCDH tSCDD Figure 2. Serial Ports ADMC300 Max Unit 0.25 tCK + 15 20 20 20 ns ns ns ns ns ns ns ns ns ns ns ABSOLUTE MAXIMUM RATINGS* Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V Supply Voltage (AVDD) . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Output Voltage Swing . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Operating Temperature Range (Ambient) . . . – 40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . +280°C *Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Model ADMC300BST ADMC300-ADVEVALKIT ADMC300-PB ORDERING GUIDE Temperature Range –40°C to +85°C Instruction Rate 25 MHz Package Description 80-Lead Plastic Thin Quad Flatpack (TQFP) Development Tool Kit Evaluation/Processor Board Package Option ST-80 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADMC300 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B –5– WARNING! ESD SENSITIVE DEVICE 5 Page ADMC300 Utility PER_RST UMASK PUT_VECTOR SMASK ADMC_COS ADMC_SIN ARCTAN RECIPROCAL SQRT LN LOG FLTONE FIXONE FPA FPS FPM FPD FPMACC PARK REV_CLARK FOR_CLARK SDIVQINT SDIVQ EXIT Table IV. ROM Utilities Address 0x07E4 0x0E21 0x0E28 0x0E35 0x0E55 0x0E5C 0x0E72 0x0E94 0x0EAA 0x0EE4 0x0EE7 0x0F03 0x0F08 0x0F0C 0x0F1B 0x0F2B 0x0F34 0x0F55 0x0F77 0x0F8B 0x0FA1 0x0FAB 0x0FB4 0x0FC6 Function Peripheral Reset. Limits Unsigned Value to Given Range. Facilitates User Setup of Vector Table. Limits Signed Value to Given Range. Cosine Function. Sine Function. Arctangent Function. Reciprocal (1/x) Function. Square Root Function. Natural Logarithm Function. Logarithm (Base 10) Function. Fixed Point to Floating Point Conversion. Floating Point to Fixed Point Conversion. Floating Point Addition. Floating Point Subtraction. Floating Point Multiplication. Floating Point Division. Floating Point Multiply and Accumulate. Forward and Reverse Park Transformation (Vector Rotation). Reverse Clark Transformation. Forward Clark Transformation. Unsigned Single Precision Division (Integer). Unsigned Single Precision Division (Fractional). Exit to Debugger after Running User Program. SYSTEM INTERFACE Figure 4 shows a basic system configuration for the ADMC300 with an external crystal and serial E2PROM for boot loading of program and data memory RAM. CLKOUT XTAL CLKIN ADMC300 DR1A RESET SCLK1 RFS1/ SROM 20pF 12.5 MHz 20pF DATA CLK RESET SERIAL E2PROM Figure 4. Basic System Configuration Clock Signals The ADMC300 can be clocked by either a crystal or a TTL- compatible clock signal. The CLKIN input cannot be halted, changed during operation or operated below the specified minimum frequency during normal operation. If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is connected to the CLKIN pin of the ADMC300. In this mode, with an external clock signal, the XTAL pin must be left unconnected. The ADMC300 uses an input clock with a frequency equal to half the instruc- tion rate; a 12.5 MHz input clock yields a 40 ns processor cycle (which is equivalent to 25 MHz). Normally instructions are executed in a single processor cycle. All device timing is relative to the internal instruction rate, which is indicated by the CLKOUT signal. Because the ADMC300 includes an on-chip oscillator circuit, an external crystal may be used instead of a clock source, as shown in Figure 4. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors as shown in Figure 4. A parallel-resonant, fundamental frequency, micro- processor-grade crystal should be used. A clock output signal (CLKOUT) is generated by the processor at the processor’s cycle rate of twice the input frequency. Reset The RESET signal initiates a master reset of the ADMC300. The RESET signal must be asserted during the power-up se- quence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock to stabilize. If RESET is activated any time after power-up, the clock continues to run and does not require stabilization time. The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is ap- plied to the processor, and for the internal phase-locked loop (PLL) to lock onto the specific crystal frequency. A minimum of 2000 CLKIN cycles ensures that the PLL has locked, but does not include the crystal oscillator start-up time. During this power-up sequence, the RESET signal should be held low. On any subsequent resets, the RESET signal must meet the mini- mum pulsewidth specification, tRSP. If an RC circuit is used to generate the RESET signal, the use of an external Schmitt trigger is recommended. The master reset sets all internal stack pointers to the empty stack condition, masks all interrupts, initializes DSP core regis- ters and performs a full reset of all of the motor control periph- erals. When the RESET line is released, the first instruction is fetched from internal program memory ROM at location 0x0800. The internal monitor code at this location then commences the boot-loading sequence over the serial port, SPORT1. Boot Loading On power-up or reset, the ADMC300 is configured so that execution begins at the internal PM ROM at address 0x0800. This starts execution of the internal monitor function that first performs some initialization functions and copies a default inter- rupt vector table to addresses 0x0000–0x005F of program memory RAM. The monitor next attempts to boot load from an external SROM or E2PROM on SPORT1 using the three wire connec- tion of Figure 4. The monitor program first toggles the RFS1/ SROM pin of the ADMC300 to reset the serial memory device. If an SROM or E2PROM is connected to SPORT1, data is clocked into the ADMC300 at a rate CLKOUT/26. Both REV. B –11– 11 Page

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