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ADMC300BST 데이터시트 PDF




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기능 High Performance DSP-Based Motor Controller
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ADMC300BST 데이터시트, 핀배열, 회로
a
High Performance DSP-Based
Motor Controller
ADMC300
TARGET APPLICATIONS
Industrial Drives, Servo Drives, Variable Speed Drives,
Electric Vehicles
FEATURES
25 MIPS Fixed-Point DSP Core
Single Cycle Instruction Execution (40 ns)
ADSP-2100 Family Code Compatible
Independent Computational Units
ALU
Multiplier/Accumulator
Barrel Shifter
Multifunction Instructions
Single Cycle Context Switch
Powerful Program Sequencer
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generators
Memory Configuration
4K ؋ 24-Bit Program Memory RAM
2K ؋ 24-Bit Program Memory ROM
1K ؋ 16-Bit Data Memory RAM
High-Resolution Multichannel ADC System
Five Independent 16-Bit Sigma-Delta ADCs
76 dB SNR Typical (ENOB > 12 Bits)
Arranged in Two Independently Clocked Banks
Differential or Single-Ended Inputs
Programmable Sample Frequency to 32.5 kHz
Flexible Synchronization of ADC and PWM Subsystems
Independent Offset Calibration for Each Channel
Two Dedicated ADC Interrupts
Internal 2.5 V Reference
Three Multiplexer Control Pins for External Expansion
Hardware or Software Convert Start
Individual Power-Down for Each Bank
Three-Phase PWM Generation Subsystem
16-Bit Dedicated PWM Generator
Edge Resolution to 40 ns
Programmable Dead Time
Programmable Minimum Pulsewidth
Double Update Mode Allows Duty Cycle
Adjustment on Half Cycle Boundaries
Special Features for Brushless DC Motors
Hardwired Polarity Control
External Dedicated Asynchronous Shutdown Pin
(PWMTRIP)
Additional Shutdown Pins in I/O System
Individual Enable/Disable of Each Output
High Frequency Chopping Mode
Transparent Transition to Overmodulation
Range with Duty Cycles of 100%
Programmable Interrupt Controller Manages Priority
and Masking of 11 Peripheral Interrupts
(Continued on Page 7)
FUNCTIONAL BLOCK DIAGRAM
ADSP-2100 BASE
ARCHITECTURE
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
PROGRAM
ROM
2K ؋ 24
PROGRAM
RAM
4K ؋ 24
MEMORY
DATA
RAM
1K ؋ 16
MOTOR CONTROL
PERIPHERALS
3
2 12
WATCH-
DOG
TIMER
PROGRAM
INTERRUPT
CONTROLLER
ENCODER
INTERFACE
EVENT
CAPTURE
TIMERS
DIGITAL
I/O
PROGRAM MEMORY ADDRESS BUS
DATA MEMORY ADDRESS BUS
PROGRAM MEMORY DATA BUS
DATA MEMORY DATA BUS
ARITHMETIC UNITS
ALU MAC SHIFTER
SERIAL PORTS
SPORT 0 SPORT 1
56
INTERVAL
TIMER
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
AUXILIARY
PWM
SIGMA-DELTA
ADCs
PWM
GENERATION
2 10
7
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000




ADMC300BST pdf, 반도체, 판매, 대치품
ADMC300–SPECIFICATIONS
ENCODER INTERFACE UNIT (VDD = AVDD = 5 V ؎ 10%, GND = AGND = 0 V, TAMB = –40؇C to +85؇C, CLKIN = 12.5 MHz, unless
otherwise noted)
Parameter
Test Conditions
Min Typ Max
Unit
fENC, MAX
Maximum Encoder Pulse Rate1
3.1 MHz
NOTES
1Assumes perfect quadrature encoder signals.
Specifications subject to change without notice.
AUXILIARY PWM OUTPUTS (VDD = AVDD = 5 V ؎ 10%, GND = AGND = 0 V, TAMB = –40؇C to +85؇C, CLKIN = 12.5 MHz, unless
otherwise noted)
Parameter
fAUXPWM
Resolution
Switching Frequency
Specifications subject to change without notice.
Test Conditions
Min Typ
8
48.8
Max
Unit
Bits
kHz
TIMING PARAMETERS
Parameter
Min
Max
Unit
Clock Signals
tCK is defined as 0.5 tCKI. The ADMC300 uses an input clock with a frequency equal
to half the instruction rate; a 12.5 MHz input clock (which is equivalent to 80 ns)
yields a 40 ns processor cycle (equivalent to 25 MHz). tCK values within the range of
0.5 tCKI period should be substituted for all relevant timing parameters to obtain
specification value.
Example: tCKH = 0.5 tCK – 10 ns = 0.5 (40 ns) – 10 ns = 10 ns.
Timing Requirements:
tCKI
tCKIL
tCKIH
CLKIN Period
CLKIN Width Low
CLKIN Width High
Switching Characteristics:
tCKL
tCKH
tCKOH
CLKOUT Width Low
CLKOUT Width High
CLKIN High to CLKOUT High
80
20
20
0.5 tCK – 10
0.5 tCK – 10
0
150
20
ns
ns
ns
ns
ns
ns
Control Signals
Timing Requirement:
tRSP RESET Width Low
5 tCK1
ns
PWM Shutdown Signals
Timing Requirements:
tPWMTPW
PWMTRIP Width Low
tPIOPWM
PIO Width Low
3 tCK
3 tCK
ns
ns
NOTES
1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
Specifications subject to change without notice.
tCKI
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
Figure 1. Clock Signals
–4– REV. B

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ADMC300BST 전자부품, 판매, 대치품
(Continued from Page 1)
Flexible Encoder Interface Subsystem
Incremental Encoder Interface
Dedicated Three Pin Interface (EIA, EIB, EIZP)
16-Bit Quadrature Counter
Input Encoder Signals to 3.1 MHz
Optional Use of Zero Marker to Reset Counter
Single North Marker Mode—Permits Single
Reset of Counter On Only First Zero Marker
Status Bits to Read Encoder Inputs
Companion Encoder Event System for Accuracy
Enhancements at Low Speeds
Associated EIU Loop Timer Permits Regular,
Programmable Updating of All Encoder and
Event Timer Registers
EIU Timer Can Also Be Used as General Purpose
Timer If Not Linked to EIU Block
Peripheral I/O (PIO) Subsystem
12-Pin Digital I/O Port
Bit Configurable as Input or Output
Each Pin Configurable as Rising Edge, Falling Edge,
High Level or Low Level Interrupt
Four Dedicated PIO Interrupts for PIO0 to PIO3
One Combined Interrupt for PIO4 to PIO11
Each I/O Line Configurable as PWM Trip Source
Two 8-Bit Auxiliary PWM Outputs
Synthesized Analog Output
Fixed 48.8 kHz Operation
0 to 99.6% Duty Cycle
Event Timer Unit
Two Event Timer Channels with Dedicated Event
Capture Blocks
Permits Timing of Duty-Cycle, Period and Frequency
Configurable Event Definition
Dedicated Event Timer Interrupt
Event Timer Readable On-the-Fly
16-Bit Watchdog Timer
Programmable 16-Bit Interval Timer with Prescaler
Two Double Buffered Synchronous Serial Ports
Four Boot Load Protocols via SPORT1
E2PROM/SROM Booting
UART Booting (SCI Compatible) with Autobaud
Feature
Synchronous Master Booting with Autobaud Feature
Synchronous Slave Booting with Autobaud Feature
Debugger Interface via SPORT1 with Autobaud (UART
and Synchronous Supported)
ROM Utilities
Full Debugger for Program Development
Preprogrammed Math Functions
Preprogrammed Motor Control Functions—Vector
Transformations
80-Lead TQFP Package
Industrial Temperature Range –40؇C to +85؇C
ADMC300
GENERAL DESCRIPTION
The ADMC300 is a single-chip DSP-based controller, suitable
for high performance control of ac induction motors, permanent
magnet synchronous motors and brushless dc motors. The
ADMC300 integrates a 25 MIPS, fixed-point DSP core with a
complete set of motor control peripherals that permits fast,
efficient development of servo motor controllers.
The DSP core of the ADMC300 is the ADSP-2171, which is
completely code compatible with the ADSP-2100 DSP family
and combines three computational units, data address genera-
tors and a program sequencer. The computational units com-
prise an ALU, a multiplier/accumulator (MAC) and a barrel
shifter. The ADSP-2171 adds new instructions for bit manipu-
lation, multiplication (X squared), biased rounding and global
interrupt masking. In addition, two flexible, double-buffered,
bidirectional, synchronous serial ports are included in the
ADMC300.
The ADMC300 provides 4K × 24-bit program memory RAM,
2K × 24-bit program memory ROM and 1K × 16-bit data
memory RAM. The program and data memory RAM can be
boot loaded through the serial port from either a serial SROM/
E2PROM, asynchronous (UART) connection, or synchro-
nous connection. The program memory ROM includes a
monitor that adds software debugging features through the
serial port. In addition, a number of pre-programmed math-
ematical and motor control functions are included in the
program memory ROM.
The motor control peripherals of the ADMC300 comprise a
high performance, five channel ADC system that uses sigma-
delta conversion technology offering a typical signal-to-noise
ratio (SNR) of 76 dB, equivalent to 12 bits. In addition, a 16-bit
center-based PWM generation unit can be used to produce high
accuracy PWM signals with minimal processor overhead. The
ADMC300 also contains a flexible encoder interface unit for
position sensor feedback, two auxiliary PWM outputs, twelve
lines of digital I/O, a two-channel event capture system, a 16-bit
watchdog timer, a 16-bit interval timer and a programmable
interrupt controller that manages all peripheral interrupts.
REV. B
–7–

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부품번호상세설명 및 기능제조사
ADMC300BST

High Performance DSP-Based Motor Controller

Analog Devices
Analog Devices

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