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ADMC330 데이터시트 PDF




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부품번호 ADMC330 기능
기능 Single Chip DSP Motor Controller
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ADMC330 데이터시트, 핀배열, 회로
a
Single Chip DSP
Motor Controller
ADMC330
FEATURES
Seven Analog Input Channels
Acquisition Synchronized to PWM Switching Frequency
Three-Phase 12-Bit PWM Generator
Programmable Deadtime and Narrow Pulse Deletion
2.5 kHz Minimum Switching Frequency
ECM Control Mode
Output Control for Space Vector Modulation
Gate Drive Block (Pulsed PWM Output Capability)
Hardwired Output Polarity Control
External Trip Input
Two 8-Bit Auxiliary PWM Timers
Synthesized Analog Output
39 kHz Frequency
0 to 99.6% Duty Cycle
Eight Bits of Digital I/O Port
Bit Configurable as Input or Output
Change of State Interrupt Support
20 MIPS Fixed Point DSP Core
Powerful Program Sequencer
Zero Overhead Looping
Conditional Instruction Execution
Independent Computational Units
ALU
Multiplier/Accumulator
Barrel Shifter
Multifunction Instructions
Single-Cycle Instruction Execution (50 ns)
Single-Cycle Context Switch
ADSP-2100 Family Code and Function Compatible with
Instruction Set Enhancements
16-Bit Watchdog Timer
Programmable 16-Bit Interval Timer with Prescaler
Two Synchronous Serial Ports
Full Debugger Interface
2 Bootstrap Protocols via Sport 1, Serial and UART
Memory Configuration
2K ؋ 24-Bit Word Program RAM
1K ؋ 16-Bit Word Data RAM
2K ؋ 24-Bit Word Program ROM
FUNCTIONAL BLOCK DIAGRAM
ADSP-2100 BASE
ARCHITECTURE
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
PROGRAM
ROM
2K ؋ 24
PROGRAM
RAM
2K ؋ 24
MEMORY
DATA
MEMORY
1K ؋ 16
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
WATCH-
DOG
TIMER
8-BIT
PIO
ARITHMETIC UNITS
ALU MAC SHIFTER
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
2 ؋ 8-BIT
AUX
PWM
ANALOG
INPUTS
12-BIT
3-PHASE
PWM
GENERAL DESCRIPTION
The ADMC330 is a low cost single chip DSP microcontroller
optimized for stand alone ac motor control applications. The
device is based on a 20 MHz fixed-point DSP core (ADSP-
2171) and a set of motor control peripherals including seven
analog input channels and a 12-bit three-phase PWM generator.
The device has two auxiliary 8-bit PWM channels and adds
expansion capability through the serial ports and an 8-bit digital
I/O port. The ADMC330 has internal 2K words program RAM,
and 1K words data RAM, which can be loaded from an external
device via the serial port. There are also 2K words of internal
program ROM, which includes a monitor that adds software
debugging features through the serial port.
The ADMC330 core combines the ADSP-2100 base architec-
ture (three computational units, data address generators and a
program sequencer) with two serial ports, a programmable
timer, extensive interrupt capabilities and on-chip program and
data memory.
In addition, the ADMC330 supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),
biased rounding and global interrupt masking, for increased
flexibility.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1997




ADMC330 pdf, 반도체, 판매, 대치품
ADMC330
Pin Pin
No. Type
1
2 I/P
3 O/P
4 SUP
5 GND
6 BIDIR
7 BIDIR
8 BIDIR
9 BIDIR
10 BIDIR
11 BIDIR
12 BIDIR
13 BIDIR
14 O/P
15 O/P
16 SUP
17 I/P
18 GND
19
20
Pin
Name
NC
VAUX3
REFOUT
VDD
GND
PIO7
PIO6
PIO5
PIO4
PIO3
PIO2
PIO1
PIO0
AUX1
AUX0
VDD
PWMTRIP
GND
NC
NC
PIN FUNCTION DESCRIPTIONS
Pin Pin
No. Type
21
22 SUP
23 GND
24
25 O/P
26 O/P
27 O/P
28 O/P
29 O/P
30 O/P
31 O/P
32
33 SUP
34 GND
35 GND
36 GND
37 GND
38 GND
39
40
Pin
Name
NC
VDD
GND
NC
PWMSYNC
CL
CH
BL
BH
AL
AH
NC
VDD
GND
GND
GND
GND
GND
NC
NC
Pin Pin
No. Type
41
42 GND
43 GND
44 I/P
45 I/P
46 I/P
47 I/P
48 GND
49 SUP
50 O/P
51 GND
52 O/P
53 BIDIR
54 BIDIR
55 I/P
56 I/P
57 BIDIR
58 BIDIR
59
60
Pin
Name
NC
GND
GND
XTAL
CLKIN
PWMPOL
RESET
GND
VDD
CLKOUT
GND
DT1
TFS1
RFS1
DR1A
DR1B
SCLK1
DT0
NC
NC
Pin Pin
No. Type
Pin
Name
61 NC
62 NC
63 BIDIR TFS0
64 BIDIR RFS0
65 BIDIR DR0
66 BIDIR SCLK0
67 SUP
VDD
68 GND GND
69 GND AGND
70 I/P
CAPIN
71 O/P
ICONST
72 GND SGND
73 I/P
V1
74 I/P
V2
75 I/P
V3
76 I/P
VAUX0
77 I/P
VAUX1
78 I/P
VAUX2
79 NC
80 NC
PIN CONFIGURATION
80-Lead Plastic Thin Quad Flatpack (TQFP)
(ST-80)
NC 61
NC 62
TFS0 63
RFS0 64
DR0 65
SCLK0 66
VDD 67
GND 68
AGND 69
CAPIN 70
ICONST 71
SGND 72
V1 73
V2 74
V3 75
VAUX0 76
VAUX1 77
VAUX2 78
NC 79
NC 80
PIN 1
IDENTIFIER
NC = NO CONNECT
ADMC330
TOP VIEW
(Not to Scale)
–4–
40 NC
39 NC
38 GND
37 GND
36 GND
35 GND
34 GND
33 VDD
32 NC
31 AH
30 AL
29 BH
28 BL
27 CH
26 CL
25 PWMSYNC
24 NC
23 GND
22 VDD
21 NC
REV. 0

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ADMC330 전자부품, 판매, 대치품
For example, the HCLK clock is 10 MHz. If 8 kHz PWM
waveforms are required, then PWMTM should be loaded
with 10 MHz/8 kHz = 1250. A value must be written to the
PWMTM register before the PWM block can be used.
The ON time of each pair of PWM waveforms, e.g., AH and AL,
is set by the integer value in the duty cycle registers PWMCHA,
PWMCHB and PWMCHC. The deadtime between the active
portions of complementary waveforms is set by the value in the
deadtime register PWMDT and is subtracted from the value in
the duty cycle register. The final deadtime adjusted fractional
duty cycle for Channel A for example is given by:
dA
=
t Aon
T PWM
=
PWMCHA PWMDT
PWMTM
The minimum pulsewidth delivered is set by the value in the
pulse deletion register PWMPD. When the calculated high or
low pulsewidth for any channel is less than PWMPD, the
switching pulse is eliminated and the outputs are saturated one
to 100% high, and the other to 100% low.
ADMC330
Output Control Unit
The Output Control Unit contains special features that allow
the ADMC330 to be easily applied for the control of electroni-
cally commutated motors (ECM) or brushless dc motors
(BDCM). In these machines, only two motor phases are required
to conduct simultaneously so that at most two power switches are
turned on at any time. In order to build up current in the motor
phases, it is necessary to turn on the upper switch in one phase and
the lower switch in another phase of the inverter.
The PWMSEG register of the ADMC330 PWM block allows
modification of the pulsewidth modulation signals from the
center-based block in order to meet the requirements for ECM
control. Three bits of the PWMSEG register (Bits 6, 7 and 8)
permit individual crossover of the three PWM signal pairs. For
example, setting Bit 8 will crossover the signals for Phase A such
that the high-side signal from the center-based block will ulti-
mately appear at the low-side output pin (AL). Conversely, the
low-side signal from the center-based block will appear at Pin AH.
AH
AL
BH
BL
CH
CL
PWMSYNC
START
PWMDT
PWMCHA
END
PWMCHB
PWMDT
PWMDT
PWMCHC
PWMDT
PWMDT
PWMTM
PWMDT
Figure 2. Three-Phase Center-Based Active Low PWM Waveforms
REV. 0
–7–

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