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PDF ADMCF327 Data sheet ( Hoja de datos )
| Número de pieza | ADMCF327 | |
| Descripción | 28-Lead Flash Memory DSP Switched Reluctance Motor Controller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a 28-Lead Flash Memory
DSP Switched Reluctance Motor Controller
ADMCF327
TARGET APPLICATIONS
Washing Machines, Refrigerator Compressors, Fans,
Pumps, Industrial Variable Speed Drives
MOTOR TYPE
Switched Reluctance Motors (SR)
FEATURES
20 MIPS Fixed-Point DSP Core
Single Cycle Instruction Execution (50 ns)
ADSP-21xx Family Code Compatible
Independent Computational Units
ALU
Multiplier/Accumulator
Barrel Shifter
Multifunction Instructions
Single Cycle Context Switch
Powerful Program Sequencer
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generators
Memory Configuration
512 ؋ 24-Bit Program Memory RAM
512 ؋ 16-Bit Data Memory RAM
4K ؋ 24-Bit Program Memory ROM
4K ؋ 24-Bit Program Flash Memory
Three Independent Programmable Sectors
Security Lock Bit
10K Erase/Program Cycles
Three-Phase 16-Bit PWM Generator
16-Bit Center-Based PWM Generator
Programmable Dead Time and Narrow Pulse Deletion
Edge Resolution to 50 ns
150 Hz Minimum Switching Frequency
Double/Single Duty Cycle Update Mode Control
Programmable PWM Pulsewidth
Special Crossover Function for Brushless DC Motors
Individual Enable and Disable for Each PWM Output
High Frequency Chopping Mode for Transformer
Coupled Gate Drives
External PWMTRIP Pin
Integrated ADC Subsystem
Six Analog Inputs
Acquisition Synchronized to PWM Switching Frequency
Internal Voltage Reference
9-Pin Digital I/O Port
Bit Configurable as Input or Output
Change of State Interrupt Support
Two 8-Bit Auxiliary PWM Timers
Synthesized Analog Output
Programmable Frequency
0% to 100% Duty Cycle
Two Programmable Operational Modes
Independent Mode/Offset Mode
16-Bit Watchdog Timer
Programmable 16-Bit Internal Timer with Prescaler
Double Buffered Synchronous Serial Port
Hardware Support for UART Emulation
Integrated Power-On Reset Function Options
28-Lead SOIC Package
FUNCTIONAL BLOCK DIAGRAM
ADSP-2100 BASE
ARCHITECTURE
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
MEMORY BLOCK
PROGRAM PROGRAM
ROM
FLASH
4K ؋ 24
4K ؋ 24
PROGRAM DATA
RAM
MEMORY
512 ؋ 24 512 ؋ 16
VREF
2.5V
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
6
ANALOG
INPUTS
16-BIT
THREE-
PHASE
PWM
ARITHMETIC UNITS
ALU MAC SHIFTER
POR
TIMER
SERIAL PORT
SPORT 1
9-BIT
PIO
2 ؋ 8-BIT WATCH-
AUX
DOG
PWM
TIMER
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
1 page  
Parameter
Serial Ports
Timing Requirements:
tSCK SCLK Period
tSCS DR/TFS/RFS Setup before SCLK Low
tSCH DR/TFS/RFS Hold after SCLK Low
tSCP SCLKIN Width
Switching Characteristics:
tCC
tSCDE
CLKOUT High to SCLKOUT
SCLK High to DT Enable
tSCDV
tRH
tRD
tSCDH
tSCDD
tTDE
tTDV
tRDV
SCLK High to DT Valid
TFS/RFSOUT Hold after SCLK High
TFS/RFSOUT Delay from SCLK High
DT Hold after SCLK High
SCLK High to DT Disable
TFS (Alt) to DT Enable
TFS (Alt) to DT Valid
RFS (Multichannel, Frame Delay Zero) to DT Valid
Specifications subject to change without notice.
ADMCF327
Min Max
Unit
100
15
20
40
0.25 tCK
0
0
0
0
0.25 tCK + 20
30
30
30
25
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLKOUT
SCLK
DR
RFSIN
TFSIN
RFSOUT
TFSOUT
DT
TFS
(ALTERNATE
FRAME MODE)
RFS
(MULTICHANNEL MODE,
FRAME DELAY 0 [MFD = 0])
tCC tCC
tSCS tSCH
t SCK
t SCP
t SCP
t RD
t RH
t SCDE
t SCDV
t TDE
t TDV
t SCDH
t SCDD
t RDV
Figure 2. Serial Port Timing
REV. 0
–5–
5 Page 
ADMCF327
VRST
VDD
VRST – VHYST
RESET
tRST
Figure 5. Power-On Reset Operation
The ADMCF327 reset sets all internal stack pointers to the
empty stack condition, masks all interrupts, clears the MSTAT
register and performs a full reset of all of the motor control periph-
erals. Following a power-up, it is possible to initiate a DSP core
and motor control peripheral reset by pulling the RESET pin
low. The RESET signal must meet the minimum pulsewidth
specification, tRSP. Following the reset sequence, the DSP
core starts executing code from the internal PM ROM located
at 0x0800.
DSP Control Registers
The DSP core has a system control register, SYSCNTL, memory
mapped at DM (0x3FFF). SPORT1 is configured as a serial
port when Bit 10 is set, or as flags and interrupt lines when this
bit is cleared. For proper operation of the ADMCF327, all other
bits in this register must be cleared.
The DSP core has a wait state control register, MEMWAIT,
memory mapped at DM (0x3FFE). The default value of this
resister is 0xFFFF. For proper operation of the ADMCF327,
this register must always contain the value 0x8000 (which is
the default).
The configuration of both the SYSCNTL and MEMWAIT reg-
isters of the ADMCF327 are shown at the end of the data sheet.
THREE-PHASE PWM CONTROLLER
Switched Reluctance Mode
The PWM generator block of the ADMCF327 is a flexible,
programmable, three-phase PWM waveform generator that
can be programmed to generate the required switching patterns
to drive a three-phase voltage source inverter for a Switched
Reluctance Motor.
The PWM generator produces three pairs of active high PWM
signals on the six PWM output pins (AH, AL, BH, BL, CH, and
CL). The six PWM output signals consist of three high side
drive signals (AH, BH, and CH) and three low side drive signals
(AL, BL, and CL). The switching frequency, dead time, and
minimum pulsewidths of the generated PWM patterns are
programmable using, respectively, the PWMTM, PWMDT, and
PWMPD registers. In addition, three registers (PWMCHA,
PWMCHB, and PWMCHC) control the duty cycles of the three
pairs of PWM signals.
Each of the six PWM output signals can be enabled or disabled
by separate output enable bits of the PWMSEG register. In
addition, three control bits of the PWMSEG register permit
crossover of the two signals of a PWM pair for easy control of
ECM or BDCM. In crossover mode, the PWM signal destined
for the high side switch is diverted to the complementary low
side output, and the signal destined for the low side switch is
diverted to the corresponding high side output signal.
In many applications, there is a need to provide an isolation barrier
in the gate-drive circuits that turn on the power devices of the
inverter. In general, there are two common isolation techniques:
optical isolation using optocouplers, and transformer isolation
using pulse transformers. The PWM controller of the ADMCF327
permits mixing of the output PWM signals with a high frequency
chopping signal to permit an easy interface to such pulse trans-
formers. The features of this gate-drive chopping mode can be
controlled by the PWMGATE register. There is an 8-bit value
within the PWMGATE register that directly controls the chopping
frequency. In addition, high frequency chopping can be indepen-
dently enabled for the high side and the low side outputs using
separate control bits in the PWMGATE register.
The PWM generator is capable of operating in two distinct modes:
single update mode or double update mode. In single update
mode, the duty cycle values are programmable only once per
PWM period, so that the resultant PWM patterns are symmetri-
cal about the midpoint of the PWM period. In the double update
mode, a second updating of the PWM duty cycle values is imple-
mented at the midpoint of the PWM period. In this mode, it is
possible to produce asymmetrical PWM patterns that produce
lower harmonic distortion in three-phase PWM inverters. This
technique also permits the closed-loop controller to change the
average voltage applied to the machine winding at a faster rate,
allowing wider closed-loop bandwidths to be achieved. The operat-
ing mode of the PWM block (single or double update mode) is
selected by a control bit in MODECTRL register.
The PWM generator of the ADMCF327 also provides an internal
signal that synchronizes the PWM switching frequency to the
A/D operation. In single update mode, a PWMSYNC pulse is
produced at the start of each PWM period. In double update
mode, an additional PWMSYNC pulse is produced at the mid-
point of each PWM period. The width of the PWMSYNC pulse
is programmable through the PWMSYNCWT register.
The PWM signals produced by the ADMCF327 can be shut
off in a number of different ways. First, there is a dedicated
asynchronous PWM shutdown pin, PWMTRIP, which, when
brought LO, instantaneously places all six PWM outputs in
the LO state. Because this hardware shutdown mechanism is
asynchronous, and the associated PWM disable circuitry does
not use clocked logic, the PWM will shut down even if the DSP
clock is not running. The PWM system may also be shut down
from software by writing to the PWMSWT register.
Status information about the PWM system of the ADMCF327
is available to the user in the SYSSTAT register. In particular,
the state of PWMTRIP is available, as well as a status bit that
indicates whether operation is in the first half or the second half
of the PWM period.
REV. 0
–11–
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADMCF327.PDF ] | |
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