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기능 DashDSP 28-Lead Flash Mixed-Signal DSP with Enhanced Analog Front End
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ADMCF341 데이터시트, 핀배열, 회로
a DashDSP28-Lead Flash Mixed-Signal DSP
with Enhanced Analog Front End
ADMCF341
FEATURES
20 MHz Fixed-Point DSP Core
Single-Cycle Instruction Execution (50 ns)
ADSP-21xx Family Code Compatibility
Independent Computational Units
ALU, Multiplier/Accumulator, Barrel Shifter
Multifunction Instructions
Single-Cycle Context Switch
Powerful Program Sequencer
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generators
Memory Configuration
512 ؋ 16-Bit Data Memory RAM
512 ؋ 24-Bit Program Memory RAM
4K ؋ 24-Bit Program Memory ROM
4K ؋ 24-Bit Program Flash Memory
Three Independent Flash Memory Sectors
3584 ؋ 24-Bit, 256 ؋ 24-Bit, 256 ؋ 24-Bit
Low-Cost Pin-Compatible ROM Option
16-Bit Watchdog Timer
Programmable 16-Bit Internal Timer with Prescaler
Two Double Buffered Serial Ports with SPI Mode Support
Integrated Power-On Reset Function
Three-Phase 16-Bit PWM Generation Unit:
16-Bit Center-Based PWM Generator
Programmable PWM Pulsewidth
Edge Resolution to 50 ns
153 Hz Minimum Switching Frequency
Double/Single Duty Cycle Update Mode Control
Individual Enable and Disable for Each PWM Output
High-Frequency Chopping Mode for Transformer
Coupled Gate Drives
External PWMTRIP Pin
Integrated 6-Channel ADC Subsystem
Three Bipolar ISENSE Inputs with Programmable
Sample-and-Hold Amplifier and Overcurrent Pro-
tection (Usable as Three Dedicated Analog Inputs)
Muxed Auxiliary Analog Inputs
Internal Voltage Reference (2.5 V)
Acquisition Synchronized to PWM Switching
Frequency
9-Pin Digital I/O Port
Bit Configurable as Input or Output
Change of State Interrupt Support
Two 16-Bit Auxiliary PWM Timers
Synthesized Analog Output
Programmable Frequency
0% to 100% Duty Cycle
Two Programmable Operational Modes
Independent Mode/Offset Mode
Motor Types
Permanent Magnet Synchronous Motors (PMSM)
Brushless DC Motors (BDCM)
AC Induction Motors (ACIM)
APPLICATIONS
Refrigerator and Air Conditioner Compressor
Washing Machines
Industrial Variable Speed Drives
HVAC
FUNCTIONAL BLOCK DIAGRAM
ADSP-21xx BASE
ARCHITECTURE
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
MEMORY BLOCK
PROGRAM PROGRAM
ROM
FLASH
4K x 24
4K x 24
PROGRAM
RAM
512 x 24
DATA
MEMORY
512 x 16
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
MOTOR CONTROL PERIPHERALS
ADC SUBSYSTEM
3
VREF
2.5V
3
ANALOG
INPUTS
ISENSE AMP
AND TRIP
SHA
TIMERS
6
16-BIT
THREE-
PHASE
PWM
ARITHMETIC UNITS
ALU MAC SHIFTER
POR
TIMER
DashDSP is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
SERIAL PORT
SPORT 0
SPORT 1
7
2 x 16-BIT
PIO AUX
PWM
92
MULTIPLEXED ON EXTERNAL PINS
WATCH-
DOG
TIMER
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002




ADMCF341 pdf, 반도체, 판매, 대치품
ADMCF341
SPECIFICATIONS (continued)
FLASH MEMORY
Parameter
Endurance
Data Retention
Program and Erase Operating Temperature
Read Operating Temperature
Specifications subject to change without notice.
Min Typ
10,000
15
0
–40
Max Unit Conditions/Comments
Cycles Cycle = Erase/Program/Verify
Years
85 C
+85 C
TIMING PARAMETERS
Parameter
Clock Signals
Signal tCK is defined as 0.5 tCKIN. The ADMCF341 uses an input clock with
a frequency equal to half the instruction rate; a 10 MHz input clock (which is
equivalent to 100 ns) yields a 50 ns processor cycle (equivalent to 20 MHz).
When tCK values are within the range of 0.5 tCKIN period, they should be
substituted for all relevant timing parameters to obtain specification value as
in the following example:
tCKH = 0.5 tCK - 10 ns = 0.5 ¥ 50 ns - 10 ns = 15 ns
Timing Requirements:
tCKIN
CLKIN Period
tCKIL
CLKIN Width Low
tCKIH
CLKIN Width High
Switching Characteristics:
tCKL CLKOUT Width Low
tCKH CLKOUT Width High
tCKOH
CLKIN High to CLKOUT High
Control Signals
Switching Characteristics
tRSP RESET Width Low
PWM Shutdown Signals
Switching Characteristics
tPWMTPW PWMTRIP Width Low
*Applies after power-up sequence is complete.
Specifications subject to change without notice.
Min
100
20
20
0.5 tCK – 10
0.5 tCK – 10
0
5 tCK*
tCK
Max
150
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
CLKIN
CLKOUT
tCKIN
tCKIH
tCKIL
tCKOH
tCKH
tCKL
Figure 1. Clock Signals
–4–
REV. 0

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ADMCF341 전자부품, 판매, 대치품
ADMCF341
GENERAL DESCRIPTION
The ADMCF341 is a low-cost, single-chip DSP-based control-
ler, suitable for permanent magnet synchronous motors, ac
induction motors, and brushless dc motors. The ADMCF341
integrates a 20 MHz, fixed-point DSP core with a complete set
of motor control and system peripherals that permits fast,
efficient development of motor controllers.
The DSP core of the ADMCF341 is completely code-compatible
with the ADSP-21xx DSP family and combines three computa-
tional units, data address generators, and a program sequencer.
The computational units are an ALU, a multiplier/accumulator
(MAC), and a barrel shifter. There are special instructions for
bit manipulation, multiplication (ϫ squared), biased rounding,
and global interrupt masking. The system peripherals are the
power-on reset circuit (POR), the watchdog timer, and two
synchronous serial ports. The serial ports are configurable and
double buffered, with hardware support for UART, SCI, and
SPI port emulation. The ADMCF341 provides 512 ϫ 24-bit
program memory RAM, 4K ϫ 24-bit program memory ROM,
4K ϫ 24-bit program FLASH memory, and 512 ϫ 16-bit data
memory RAM. The user code can be stored and executed from
the flash memory. The program and data memory RAM can be
used for dynamic data storage or can be loaded through the
serial port from an external device as in other ADMCxxx family
parts. The program memory ROM contains a monitor function
as well as useful routines for erasing, programming, and verifying
the flash memory.
The motor control peripherals of the ADMCF341 provide a
12-bit analog data acquisition system with six analog input
channels with three dedicated ISENSE inputs (combining internal
amplification, sampling, and overcurrent PWM shutdown
features) and an internal voltage reference. In addition, a three-
phase, 16-bit, center-based PWM generation unit can be used
to produce high accuracy PWM signals with minimal processor
overhead. The ADMCF341 also contains two 16-bit auxiliary
PWM timer outputs and nine lines of digital I/O.
Because the ADMCF341 has a limited number of pins, functions
such as the auxiliary PWM timers and the serial communication
ports are multiplexed with the nine programmable digital input/
output (PIO) pins. The pin functions can be independently
selected to allow maximum flexibility for different applications.
DSP CORE ARCHITECTURE OVERVIEW
Figure 3 is an overall block diagram of the DSP core of the
ADMCF341. The flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera-
tions in parallel. In one processor cycle (50 ns with a 10 MHz
CLKIN) the DSP core can:
Generate the next program address
Fetch the next instruction
Perform one or two data moves
Update one or two data address pointers
Perform a computational operation
This all takes place while the processor continues to:
Receive and transmit through the serial ports
Decrement the interval timer
Generate three-phase PWM waveforms for a power inverter
Generate two signals using the 16-bit auxiliary PWM timers
Acquire four analog signals
Decrement the watchdog timer
DATA
ADDRESS
GENERATOR
#1
DATA
ADDRESS
GENERATOR
#2
INSTRUCTION
REGISTER
PROGRAM
SEQUENCER
14
14
24
BUS
EXCHANGE
16
PM ROM
4K ؋ 24
PM RAM
512 ؋ 24
FLASH
PROGRAM
MEMORY
4K ؋ 24
PMA BUS
DMA BUS
PMD BUS
DMD BUS
DM RAM
512 ؋ 16
INPUT REGS
ALU
OUTPUT REGS
INPUT REGS
MAC
OUTPUT REGS
16
R BUS
INPUT REGS
SHIFTER
OUTPUT REGS
CONTROL
LOGIC
COMPANDING
CIRCUITRY
Figure 3. DSP Core Block Diagram
TIMER
TRANSMIT REG
RECEIVE REG
SERIAL
PORT
6
REV. 0
–7–

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