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ADP1147 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 ADP1147
기능 High Efficiency Step-Down Switching Regulator Controllers
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ADP1147 데이터시트, 핀배열, 회로
a
High Efficiency Step-Down
Switching Regulator Controllers
ADP1147-3.3/ADP1147-5
FEATURES
Greater Than 95% Efficiency
Current Mode Switching Architecture Provides
Superior Load and Line Transient Response
Wide Input Voltage Range 3.5 V* to 16 V
User Defined Current Limit
Short Circuit Protection
Shutdown Pin
Low Dropout Voltage
Low Standby Current 160 A typ
Low Cost
Available in 8-Lead PDIP or 8-Lead SOIC
APPLICATIONS
Portable Computers
Modems
Cellular Telephones
Portable Equipment
GPS Systems
Handheld Instruments
GENERAL DESCRIPTION
The ADP1147 is part of a family of High Efficiency Step-Down
Switching Regulators. These regulators offer superior load and
line transient response, a user defined current limit and an
automatic power savings mode. The automatic power savings
mode is used to maintain efficiency at lower output currents.
The ADP1147 incorporates a constant off-time, current mode
switching architecture to drive an external P-channel MOSFET
at frequencies up to 250 kHz. Constant off-time switching gen-
erates a constant ripple current in the external inductor. This
results in a wider input voltage operating range of 3.5 V* to
16 V, and a less complex circuit design.
*3.5 volt operation is for the ADP1147-3.3.
VIN (5.2V TO 12V)
+
1F
+ CIN
100F
P-CHANNEL
IRF7204
L*
50H
D1
30BQ040
RSENSE**
0.05
VOUT
5V/2A
+ COUT
390F
0V = NORMAL
1.5V = SHUTDOWN
VIN
P-DRIVE
CC RC
3300pF 1k
ADP1147
SHUTDOWN
ITH SENSE(+)
CT SENSE(–)
CT GND
470pF
1000pF
*COILTRONICS CTX 50–2MP
**KRL SL-1-C1-0R050J
SHUTDOWN
Figure 1. High Efficiency Step-Down Converter
(Typical Application)
FUNCTIONAL BLOCK DIAGRAM
VIN P-DRIVE GROUND SENSE(+) SENSE(–)
ADP1147
SLEEP
S VTH2
VTH1
1
QR
S
T
2
R
QS
V
B
C 10mV to 150mV
13k
G
VOS
1.25V
5pF
100k
OFF-TIME VIN
CONTROL SENSE(–)
REFERENCE
CT ITH SHUTDOWN
A very low dropout voltage with excellent output regulation can
be obtained by minimizing the dc resistance of the Inductor, the
RSENSE resistor, and the RDS(ON) of the P-MOSFET. The power
savings mode conserves power by reducing switching losses at
lower output currents. When the output load current falls below
the minimum required for the continuous mode the ADP1147
will automatically switch to the power savings mode. It will remain
in this mode until the inductor requires additional current or the
sleep mode is entered. In sleep mode with no load the standby
power consumption of the device is reduced to 2.0 mW typical
at VIN = 10 V.
For designs requiring even greater efficiencies refer to the
ADP1148 data sheet.
100
95 VIN = 6 VOLTS
90
VIN = 10 VOLTS
85
80
75
70
65
60
1 10 100 1k 10k
LOAD CURRENT – mA
Figure 2. ADP1147-5 Typical Efficiency, Figure 1 Circuit
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998




ADP1147 pdf, 반도체, 판매, 대치품
ADP1147-3.3/ADP1147-5–Performance Characteristics
200 1000
1000
VSENSE = VOUT = +5V
L = 50H
RSENSE = 0.02
800 800
150 L = 25H
RSENSE = 0.02
600 600
100 VIN = +12V
400 400
L = 50H
50
200 VIN = +7V
VIN = +10V
RSENSE = 0.05
200
0
01 234 5
MAXIMUM OUTPUT CURRENT – Amps
Figure 3. Selecting RSENSE vs.
Maximum Output Current
0
0 100 200 300
FREQUENCY – kHz
Figure 4. Operating Frequency vs.
Timing Capacitor
0
01 234 5
(VIN – VOUT) VOLTAGE – Volts
Figure 5. Selecting Minimum Output
Capacitor vs. (VIN – VOUT) and Inductor
100
GATE CHARGE
95
ADP1147 IQ
90
85
I2R
SCHOTTKY
DIODE
80
10m
30m
0.1 0.3
IOUT – Amps
1
3
Figure 6. Typical Efficiency Losses
5.11
5.10
FIGURE 1 CIRCUIT
5.09
5.08
5.07
VIN = 6 VOLTS
5.06
5.05
5.04
VIN = 12 VOLTS
5.03
5.02
0
400 800 1200 1600 2000
LOAD CURRENT – mA
Figure 9. Load Regulation
100
FIGURE 1 CIRCUIT
95
1 AMP
90
85 0.1 AMP
80
75
70
5 8 11 14 17 20
INPUT VOLTAGE – Volts
Figure 7. Efficiency vs. Input Voltage
5.11
FIGURE 1 CIRCUIT
5.10
5.09
100mA
5.08
5.07
5.06 300mA
5.05
5.04
5.03
4
1 AMP
8 12
INPUT VOLTAGE – V
16
Figure 8. ADP1147-5 Output Voltage
vs. Input Voltage
1.6
1.4
ACTIVE MODE
1.2
1.0
0.8
0.6
0.4
0.2 SLEEP MODE
0
4 6 8 10 12 14 16 18 20
INPUT VOLTAGE – Volts
Figure 10. DC Supply Current
40
35
VSHUTDOWN = +2V
30
25
20
15
10
5
0
4 6 8 10 12 14 16 18
INPUT VOLTAGE – Volts
Figure 11. Supply Current in
Shutdown
20
–4– REV. 0

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ADP1147 전자부품, 판매, 대치품
ADP1147-3.3/ADP1147-5
APPLICATIONS
The ADP1147 family of regulators incorporate a current mode,
constant off-time architecture to switch an external P-channel
MOSFET. The external MOSFET can be switched at frequen-
cies up to 250 kHz. The switching frequency of the device is
determined by the value selected for capacitor CT.
A regulated output voltage is maintained by the feedback volt-
age at the SENSE(–) pin. The SENSE(–) pin is connected to an
internal voltage divider. The voltage from this internal divider is
fed to comparator V, and gain block G. It is then compared to
an internal 1.25 volt reference.
The ADP1147 is capable of maintaining high levels of efficiency
by automatically switching between the power saving and con-
tinuous modes. The internal R-S flip-flop #2 controls the device
in the power saving mode, and gain block G assumes control
when the device is in the continuous mode of operation.
During the P-MOSFET on time, the voltage developed across
RSENSE is monitored by the SENSE(–) and SENSE(+) pins of
the device. When this voltage reaches the threshold level of
comparator C the output trips, switching the P drive to VIN, and
turns the external P-MOSFET off. At this point capacitor CT
begins to discharge at a rate that is determined by the off-time
controller. The CT discharge current is proportional to the
voltage measured at the SENSE(–) pin. When the voltage on
cap CT decays to the threshold voltage (VTH1), comparator T
switches and sets R-S flip-flop #1. This forces the P-drive out-
put low, and turns on the P-MOSFET. The sequence is then
repeated. As the load current is increased, the output voltage
starts to drop. This causes the gain circuit to raise the threshold
of the current comparator, and the load current is now tracked.
When load currents are low, comparator B sets the R-S flip-flop
#2 and asserts the power savings mode of operation. Compara-
tor B monitors the voltage developed across RSENSE. As the load
current decreases to 50% of the designed inductor ripple cur-
rent, the voltage reverses polarity. This reversal causes compara-
tor B to trip, setting the Q-bar output of R-S flip-flop #2 to a
logic zero, and interrupts the cycle by cycle operation of the
output. The output storage capacitors are then slowly discharged
by the load. When the output cap voltage decays to the VOS level
of comparator V, it resets flip-flop #2, and the normal cycle by
cycle mode of operation resumes. If load currents are extremely
small, the time it takes for flip-flop #2 to reset increases. During
the extended wait for reset period, capacitor CT will discharge
below the value of VTH2 causing comparator S to trip. This
forces the internal sleep bar low and the device enters the sleep
mode. A significant amount of the IC is disabled during the
sleep mode, reducing the ground current from 1.6 mA to
160 µA, typical. In sleep mode the P-MOSFET is turned off
until additional inductor current is required. The sleep mode is
terminated when flip-flop #2 is reset.
Due to the constant off-time architecture, the input voltage has
an effect on the device switching frequency. To limit the effects
of this variation in frequency the discharge current is increased
as the device approaches the dropout voltage of VIN +1.5 V. In
the dropout mode the P-MOSFET is constantly turned on.
Determining the Output Current and the Value for RSENSE
The value selected for RSENSE is determined by the required
output current. The current comparator C has a threshold volt-
age range of 10 mV/RSENSE to 150 mV/RSENSE maximum. This
threshold sets the peak current in the external inductor and
yields a maximum output current of:
I MAX
= IPEAK
I RIPPLE
2
pp
The resistance values for RSENSE can range from 20 mto
200 m. A graph for selecting RSENSE vs. the maximum out-
put current is shown in Figure 3.
The value of RSENSE can be determined by using the following
equation:
RSENSE (in m) = 100/IMAX
This equation allows for a design margin due to component
variations.
The following equations are used to approximate the trip point
for the power savings mode and the peak short circuit current.
IPOWER SAVINGS ~ 5 mV/RSENSE + VO tOFF/2L
ISC(PK) = 150 mV/RSENSE
The ADP1147 automatically increases the tOFF time when a
short circuit condition is encountered. This allows sufficient
time for the inductor to decay between switching cycles. Due to
the resulting inductor ripple current the average short circuit
current ISC(AVG) is reduced to approximately IMAX.
Determining the Operating Frequency and Selecting Values
for CT and L
The ADP1147 incorporates a constant off-time architecture to
switch an external P-MOSFET. The off-time (tOFF) is deter-
mined by the value of the external timing cap CT. When the
P-MOSFET is turned on the voltage across CT is charged to
approximately 3.3 volts. During the switch off-time the voltage
on CT is discharged by a current that is proportional to the
voltage level of VOUT. The voltage across CT is representative of
the current in the inductor, which decays at a rate that is pro-
portional to VOUT. Due to this relationship the value of the
inductor must track the value selected for CT.
The following equation is used to determine the desired con-
tinuous mode operating frequency:
1VOUT +V D
CT
=
V IN +V D
1.3 ×104 × f
VD = the voltage drop across the Schottky diode.
The graph in Figure 4 can be used to help determine the capaci-
tance value of CT vs. the operating frequency and input voltage.
The P-MOSFET gate charge losses increase with the operating
frequency and results in lower efficiency (see the Efficiency
section).
REV. 0
–7–

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