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부품번호 ADP1148AR-33 기능
기능 High Efficiency Synchronous Step-Down Switching Regulators
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ADP1148AR-33 데이터시트, 핀배열, 회로
a
High Efficiency Synchronous
Step-Down Switching Regulators
ADP1148, ADP1148-3.3, ADP1148-5
FEATURES
Operation From 3.5 V to 18 V Input Voltage
Ultrahigh Efficiency > 95%
Low Shutdown Current
Current Mode Operation for Excellent Line and Load
Transient Response
High Efficiency Maintained Over Wide Current Range
Logic Controlled Micropower Shutdown
Short Circuit Protection
Very Low Dropout Operation
Synchronous FET Switching for High Efficiency
Adaptive Nonoverlap Gate Drives
APPLICATIONS
Notebook and Palmtop Computers
Portable Instruments
Battery Operated Digital Devices
Industrial Power Distribution
Avionics Systems
Telecom Power Supplies
GPS Systems
Cellular Telephones
GENERAL DESCRIPTION
The ADP1148 is part of a family of synchronous step-down
switching regulator controllers featuring automatic sleep mode
to maintain high efficiencies at low output currents. These
devices drive external complementary power MOSFETs at
switching frequencies up to 250 kHz using a constant off-time
current-mode architecture.
FUNCTIONAL BLOCK DIAGRAM
ADP1148
ADJUSTABLE
PWR SIGNAL
VERSION
VIN P-DRIVE N-DRIVE GND GND SENSE(+) VFB SENSE(–)
31
14 12 11
89
7
SLEEP
S
VTH2
4
CT
NON-OVERLAP
DRIVE
1
QR
VTH1
S
T
2
R
QS
C
10mV to
150mV
OFF-TIME
CONTROL
VIN
SENSE(–)
VFB
6
ITH
V
B
13k
G
1.25V 100k
REFERENCE
10
SHUTDOWN
5
INT VCC
The constant off-time architecture maintains constant ripple
current in the inductor, easing the design of wide input range
converters. Current-mode operation provides excellent line and
load transient response. The operating current level is user
programmable via an external current sense resistor.
The ADP1148 incorporates automatic Power Saving Sleep
Mode operation when load currents drop below the level re-
quired for continuous operation. In sleep mode, standby power
is reduced to only about 2 mW at VIN = 10 V. In shutdown,
both MOSFETs are turned off.
+
1F
VIN (5.2V TO 18V)
10nF
VIN
INT VCC
P-DRIVE
0V = NORMAL
>1.5V = SHUTDOWN
ADP1148
SHUTDOWN
ITH SENSE(+)
RC
1k
CC
3300pF
CT SENSE(–)
CT N-DRIVE
470pF
S-GND P-GND
TYPICAL APPLICATIONS
CIN +
100F
P-CH
IRF7204
L* RSENSE**
62H 0.05
VOUT
5V/2A
1000pF
N-CH
IRF7403
C1
10BQ040
+ COUT
390F
*COILTRONICS CTX-68-4
**KRL SL-1-C1-0R050L
100
VIN = 6V
95
VIN = 10V
90
85
80
75
FIGURE 1 CIRCUIT
70
0.02
0.2
LOAD CURRENT – A
2
Figure 1. High Efficiency Step-Down Converter
Figure 2. ADP1148-5 Typical Efficiency
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1997




ADP1148AR-33 pdf, 반도체, 판매, 대치품
ADP1148, ADP1148-3.3, ADP1148-5
PIN FUNCTION DESCRIPTIONS
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Mnemonic
Function
P-Channel Drive High Current Gate Drive for Top P-Channel MOSFET. The voltage swing at Pin 4 is from VIN to
ground.
NC No Connection.
VIN
CT
Int VCC
Input Voltage.
External Capacitor CT from Pin 4 to Ground Sets the Operating Frequency. The frequency is also
dependent on the ratio VOUT/VIN.
Internal Supply Voltage, Nominally 3.3 V. Must be decoupled to signal ground. Do not externally load
this pin.
ITH
Sense–
Error Amplifier Decoupling Point. The current comparator threshold increases with the Pin 7 voltage.
Connects to internal resistive divider that sets the output voltage in ADP1148-3.3 and ADP1148-5
versions. Pin 7 is also the (–) input for the current comparator.
Sense+
VFB
The (+) Input for the Current Comparator. A built-in offset between Pins 7 and 8, in conjunction with
RSENSE, sets the current trip threshold.
For the ADP1148 adjustable version, Pin 9 serves as the feedback pin from an external resistive divider
used to set the output voltage. On ADP1148-3.3 and ADP1148-5 versions, this pin is not used.
Shutdown
Taking Pin 10 of the ADP1148, ADP1148-3.3 or ADP1148-5 high holds both MOSFETs off. Must be
at ground potential for normal operation.
Signal GND
Power GND
NC
Small Signal Ground. Must be routed separately from other grounds to the (–) terminal of COUT.
Driver Power Ground. Connects to source of N-channel MOSFET and the (–) terminal of CIN.
No Connection.
N-Channel Drive High Current Drive for bottom N-channel MOSFET. The voltage swing at Pin 13 is from ground to
VIN.
PIN CONFIGURATIONS
14-Lead Plastic DIP
14-Lead Plastic SO
P-DRIVE 1
14 N-DRIVE
NC 2
13 NC
VIN 3 ADP1148 12 POWER GND
CT 4 TOP VIEW 11 SIGNAL GND
(Not to Scale)
INT VCC 5
10 SHUTDOWN
ITH 6
9 VFB*
SENSE(–) 7
8 SENSE(+)
NC = NO CONNECT
*FIXED OUTPUT VERSIONS = SD1
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP1148, ADP1148-3.3, ADP1148-5 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4– REV. A

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ADP1148AR-33 전자부품, 판매, 대치품
ADP1148, ADP1148-3.3, ADP1148-5
APPLICATIONS
The ADP1148 uses a current-mode, constant off-time structure
to switch a pair of external complementary N- and P-channel
MOSFETs. The operating frequency of the device is deter-
mined by the value of the external capacitor connected to the
CT pin.
The output voltage is sensed by an internal voltage divider which is
connected to the Sense(–) pin (ADP1148-3.3 and AD1148-5) or
an external voltage divider returned to VFB (ADP1148). A voltage
comparator V, and a gain block G compare the values of the
divided output voltage with a reference voltage of 1.25 V.
To maximize the efficiency, the ADP1148 automatically switches
between two operational modes, power-saving and continuous.
The Flip-Flop 1 is the main control element when the device is
in its power-saving mode while the gain block is the main con-
trol when the output voltage moves to continuous mode. During
the continuous mode of the PMOS switch on-cycle, the current
comparator C, monitors the voltage between Sense(–) and
Sense(+). When the voltage level reaches the threshold level, the
P drive output is switched to VIN which turns off the P-channel
MOSFET. The timing capacitor CT is now able to discharge at
a rate determined by the off-time controller. The discharge
current is made to be proportional to the value of the output
voltage (measured at the Sense(–) pin) to model the inductor
current which decays at a rate which is proportional to the out-
put voltage. While the timing capacitor is discharging, the N
drive output goes to VIN , turning on the N-channel MOSFET.
When the voltage level on the timing capacitor has discharged to
the threshold voltage level VTH1, comparator T switches setting
Flip-Flop 1. This forces the N drive to go off and the P drive
output low and subsequently turns the P-channel MOSFET on.
The sequence is then repeated. As load current increases, the
output voltage starts to reduce. This results in the output of the
gain circuit increasing the level of the current comparator thresh-
old, thus tracking the load current.
At very low load currents the power-saving sequence will be
interrupted by the Set of Flip-Flop 2, by voltage comparator B,
which also monitors the voltage across RSENSE. When the load
current decreases to half the designed inductor ripple current,
the voltage across RSENSE will reverse polarity. When this hap-
pens, comparator B will set the Q-bar output of Flip-Flop 2,
which will go to logic zero state and interrupt the cycle-by-cycle
operation and inhibit the output FET-driver. The output of the
power supply storage capacitor will slowly be drained by the
load and the output voltage starts decreasing. When this
decreased voltage exceeds the VOS of comparator V, this in turn
will reset Flip-Flop 2, and normal cycle-by-cycle operation will
resume. If the load is very small, it will take a long time for Flip-
Flop 2 to reset, and during that time the oscillator capacitor
may discharge below VTH2. At the point at which the timing
capacitor discharges below VTH2, comparator S trips causing the
internal sleep-bar to go low. The circuit is now in sleep mode
and the N-channel Power MOSFET remains turned off. While
the circuit remains in this mode, a significant amount of the
circuit of the IC is turned off dropping the ground current from
approximately 1.6 mA to a level of 160 µA. In this state the load
current is supplied by the output capacitor. The sleep mode is
also terminated by the reset of Flip-Flop 2.
To prevent both the external MOSFETs from ever being turned
on simultaneously, feedback is incorporated to sense the state of
the driver output pins.
Before the N drive output can go high, the P drive output must
also be high. Likewise, the P drive output is unable to go low
while the N drive output is high. By utilizing a constant off-time
structure, the device operation is a function of the input voltage.
To limit the effect of frequency variation as the device approaches
dropout, the controller begins to increase the discharge current
as VIN drops below VOUT +1.5 V. While the device is in drop-
out, the P-channel MOSFET is on constantly.
RSENSE Selection For Output Current
The choice of RSENSE is based on the required output current.
The ADP1148 current comparator has a threshold range which
extends from 0 mV to a maximum of 150 mV/RSENSE. The
current comparator threshold sets the peak of the inductor cur-
rent, yielding a maximum output current IMAX equal to the peak
value less half the peak-to-peak ripple current. The ADP1148
operates effectively with values of RSENSE from 20 mto
200 m. A graph for selecting RSENSE versus maximum output
current is given in Figure 3. Solving for RSENSE and allowing a
margin for variations in the ADP1148 and external component
values yields:
RSENSE = 100 mV/IMAX
The peak short circuit current, (ISC(PK)) tracks IMAX. Once
RSENSE has been chosen, ISC(PK) can be predicted from the fol-
lowing equation:
ISC(PK) = 150 mV/RSENSE
The load current, below which power-saving mode commences
(IPOWER-SAVING) is determined by the offset in comparator B and
the value of the inductor chosen. Comparator B is designed to
have approximately 5 mV offset. This offset and the inductor
can now be used to predict the power saving mode current as
follows:
IPOWER-SAVING ~ 5 mV/RSENSE + VO × tOFF /2 L
The ADP1148 automatically extends tOFF during a short circuit
to provide adequate time for the inductor current to decay be-
tween switch cycles. The resulting ripple current causes the
average short circuit current, ISC(AVG), to be lowered to approxi-
mately IMAX.
L and CT Selection for Operating Frequency
The ADP1148 uses a constant off-time architecture with tOFF
determined by an external timing capacitor CT. Each time the
P-channel MOSFET switch turns on, the voltage on CT is reset
to approximately 3.3 V. During the off time, CT is discharged by
a current which is proportional to VOUT. The voltage on CT is
analogous to the current in inductor L, which likewise decays at
a rate proportional to VOUT. Therefore, the inductor value must
track the timing capacitor value.
The value of CT is calculated from the preferred continuous
mode operating frequency:
CT = 1/2.6 × 104 × f
Assumes VIN = 2 VOUT (Figure 1 circuit).
A graph for selecting CT versus frequency including the effects
of input voltage is given in Figure 5.
*Component, voltage, current, etc., values are in SI-units (international standard)
unless otherwise indicated.
REV. A
–7–

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ADP1148AR-33

High Efficiency Synchronous Step-Down Switching Regulators

Analog Devices
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