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PDF ADP3026 Data sheet ( Hoja de datos )
| Número de pieza | ADP3026 | |
| Descripción | High-Efficiency Notebook Computer Power Supply Controller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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PRELIMINARY TECHNICAL DATA
a
High-Efficiency Notebook Computer
Power Supply Controller
Preliminary Technical Data
ADP3026
FEATURES
Wide Input Voltage Range: 6.5 V to 25 V
High Conversion Efficiency > 96%
Integrated Current Sense—No External Resistor Re-
quired
Low Shutdown Current: 14 A (Typical)
Voltage Mode PWM with Input Feed Forward for Fast
Line Transient Response
Dual Synchronous Buck Controllers with PWM/
Power-Saving Mode Operation
Built-In Gate Drive Boost Circuit for Driving Exter-
nal
N-Channel MOSFETs
Two Fixed Output Voltages: 3.3 V, 5 V
PWM Frequency: 300 kHz
Extensive Circuit Protection Functions
28-Lead TSSOP Package
APPLICATIONS
Notebook Computers and PDAs
Portable Instruments
General Purpose DC-DC Converters
GENERAL DESCRIPTION
The ADP3026 is a highly efficient dual synchronous buck
switching regulator controller optimized for converting the
battery or adapter input into the system supply voltages re-
quired in notebook computers. The ADP3026 uses a
dual-mode PWM/Power Saving Mode architecture to maintain
efficiency over a wide load range.
The ADP3026 provides accurate and reliable short circuit
protection using an internal current sense circuit, which re-
duces cost and increases overall efficiency. Other protection
features include programmable soft-start, UVLO, and inte-
grated output undervoltage/overvoltage protection.
VIN
6.5V TO 25V
Q3
L2
5V
Q4
FUNCTIONAL BLOCK DIAGRAM
ADP3026
5V LINEAR
REF
5V
SMPS
3.3V
SMPS
SS5
PWRGD
POWER-ON
RESET
Q1
L1
Q2
3.3V
SS3
REV. PrB
3/12/02
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
1 page  
PRELIMINARY TECHNICAL DATA
ADP3026
ABSOLUTE MAXIMUM RATINGS*
VIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +27 V
AGND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V
INTVCC . . . . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to +6 V
BST5, BST3 to PGND . . . . . . . . . . . . . . . . . –0.3 V to +32 V
BST5 to SW5 . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
BST3 to SW3 . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
CS5, CS3 . . . . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to VIN
SW3, SW5 to PGND . . . . . . . . . . . . . . . . –2 V to VIN + 2 V
SD . . . . . . . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to +27 V
DRVL5/3 to PGND . . . . . . . . –0.3 V to (INTVCC + 0.3 V)
DRVH5/3 to SW5/3 . . . . . . . . –0.3 V to (INTVCC + 0.3 V)
All Other Inputs and Outputs
. . . . . . . . . . . . . . . . . . AGND – 0.3 V to INTVCC + 0.3 V
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98°C/W
Operating Ambient Temperature Range . . . . –40°C to +85°C
Junction Temperature Range . . . . . . . . . . . . –40°C to +150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
*This is a stress rating only; operation beyond these limits can cause the device
to be permanently damaged.
PIN CONFIGURATION
CS5 1
FB5 2
EAN5 3
EAO5 4
SS5 5
ADP3026
TOP VIEW
(Not to Scale)
CLSET5 6
REF 7
AGND 8
CLSET3 9
SS3 10
EAO3 11
EAN3 12
FB3 13
CS3 14
28 BST5
27 DRVH5
26 SW5
25 DRVL5
24 PGND
23 SD
22 INTVCC
21 VIN
20 DRVL3
19 SW3
18 DRVH3
17 BST3
16 CPOR
15 PWRGD
Model
ADP3026ARU
ORDERING GUIDE
Temperature Range
–40°C to +85°C
Package Description
Thin Shrink Small Outline
Package Option
RU-28
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although this device features proprietary ESD protection circuitry, permanent damage may oc-
cur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precau-
tions are recommended to avoid performance degradation or loss of functionality.
REV. PrB
–5–
5 Page 
PRELIMINARY TECHNICAL DATA
ADP3026
Shutdown (SD)
Holding SD = GND low will put the ADP3026 into
ultralow current shutdown mode. For automatic start-up,
SD can be tied directly to VIN.
Soft-Start and Power-Up Sequencing (SS)
SS3 and SS5 are soft-start pins for the two controllers. A
2.5 µA pull-up current is used to charge an external soft-
start capacitor. Power-up sequencing can easily be done by
choosing different capacitance. When SS3/SS5 < 0.6 V, the
two switching regulators are turned off. When 0.6 V < SS5/
SS3 < 1.8 V, the regulators start working in soft-start mode.
When SS3/SS5 > 1.8 V, the regulators are in normal oper-
ating mode. The controllers are forced to stay in PWM
mode during the soft-start period. The minimum soft-start
time (~20 µs) is set by an internal capacitor. Table II shows
the ADP3026 operating modes.
Current Limiting (CLSET)
A cycle-by-cycle current limiting scheme is used by monitor-
ing current through the top N-channel MOSFET when it is
turned on. By measuring the voltage drop across the high-side
MOSFET VDS(ON), the external sense resistor can be de-
leted. The current limit value can be set by CLSET. When
CLSET = Floating, the maximum VDS(ON) = 72 mV at
room temperature; when CLSET = 0 V, the maximum
VDS(ON) = 300 mV at room temperature. An external resistor
can be connected between CLSET and AGND to choose a
value between 72 mV and 300 mV. The relationship between
the external resistance and the maximum VDS(ON) is:
VDS(ON )MAX
=
72 mV
(110K + REXT )
(26K + REXT )
(1)
The temperature coefficient of RDS(ON) of the N-channel
MOSFET is canceled by the internal current limit circuitry,
so that an accurate current limit value can be obtained
over a wide temperature range. In PSV mode, the current
limit value is reduced to about 1/4 of the value in PWM
mode to reduce the interference noise to other components
on the PC board.
Output Undervoltage Protection
Each switching controller has an undervoltage protection
circuit. When the current flowing through the high-side
MOSFET reaches the current limit continuously for eight
clock cycles, and the output voltage is below 20% of the
nominal output voltage, both controllers will be latched
off and will not restart until SD or SS3/SS5 is toggled, or
until VIN is cycled below 4 V. This feature is disabled during
soft start.
Output Overvoltage Protection
Both converter outputs are continuously monitored for ov-
ervoltage. If either output voltage is higher than the nominal
output voltage by more than 20%, both converter’s high-side
gate drivers (DRVH5/3) will be latched off, and the low-
side gate drivers will be latched on, and will not restart until
SD or SS5/SS3 are toggled, or until VIN is cycled below 4
V. The low-side gate driver (DRVL) is kept high when
the controller is in off-state and the output voltage is less
than 93% of the nominal output voltage. Discharging the
output capacitors through the main inductor and low-side
N-channel MOSFET will cause the output to ring. This
will make the output momentarily go below GND. To
prevent damage to the circuit, use a reverse-biased 1 A
Schottky diode across the output capacitors to clamp the
negative surge.
Power Good Output (PWRGD)
The ADP3026 also provides a PWRGD signal for the mi-
croprocessor. During start-up, the PWRGD pin is held low
until 5 V output is within –3% of its preset voltage. Then,
after a time delay determined by an external timing ca-
pacitor connected from CPOR to GND, PWRGD will be
actively pulled up to INTVCC by an external pull-up resis-
tor. This delay can be calcualated by:
Td = 1.2V ×CCPOR
1µA
(2)
CPOR can also be used as a manual reset (MR) function.
When the 5 V output is lower than the preset voltage by
more than 7%, PWRGD is immediately pulled low.
APPLICATION INFORMATION
A typical notebook PC application circuit using the
ADP3026 is shown in Figure 2. Although the component val-
ues given in Figure 3 are based on a 5 V @ 4 A /3.3 V @
4 A design, the ADP3026 output drivers are capable of
SD
Low
High
High
High
High
High
Table II. Operating Modes
SS5
X
SS5 < 0.6 V
0.6 V < SS5 < 1.8 V
1.8 V < SS5
X
X
SS3
X
SS3 < 0.6 V
X
X
0.6 V < SS3 < 1.8 V
1.8 V < SS3
Mode
Shutdown
Standby
Run
Run
Run
Run
Description
All Circuits Turned Off
5 V and 3.3 V Off; INTVCC = 5 V, REF = 0.8 V
5 V in Soft Start
5 V in Normal Operation
3.3 V in Soft Start
3.3 V in Normal Operation
REV. PrB
–11–
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ADP3026.PDF ] | |
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