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부품번호 ADP3153 기능
기능 5-Bit Programmable Dual Power Supply Controller for Pentium II Processor
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ADP3153 데이터시트, 핀배열, 회로
a
FEATURES
5-Bit Digitally Programmable 1.8 V to 3.5 V Output
Voltage
Dual N-Channel Synchronous Driver
Total Output Accuracy ؎1% (0؇C to +70؇C)
High Efficiency
Current-Mode Operation
Short Circuit Protection
Power Good Output
Overvoltage Protection Crowbar
On-Board Linear Regulator Controller
VRM 8.2 Compatible
Narrow Body TSSOP 20-Lead Package
APPLICATIONS
Desktop PC Power Supply for:
Pentium II Processor
Deschutes Processor
Pentium Pro Processor
Pentium Processor
AMD–K6 Processor
VRM Modules
5-Bit Programmable Dual
Power Supply Controller
for Pentium® II Processor
ADP3153
GENERAL DESCRIPTION
The ADP3153 is a highly efficient synchronous switching regu-
lator controller and a linear regulator controller. The switching
regulator controller is optimized for Pentium II and Deschutes
Processor applications where 5 V is stepped down to a digitally
controlled output voltage between 1.8 V and 3.5 V. Using a 5-bit
DAC to read a voltage identification (VID) code directly from
the processor, the ADP3153 uses a current mode constant off-
time architecture to generate its precise output voltage.
The ADP3153 drives two N-channel MOSFETS in a synchro-
nous rectified buck converter, at a maximum switching fre-
quency of 250 kHz. Using the recommended loop compensation
and guidelines, the ADP3153 provides a dc/dc converter that
meets Intel’s stringent transient specifications with a minimum
number of output capacitors and smallest footprint. Addition-
ally, the current mode architecture also provides guaranteed
short circuit protection and adjustable current limiting.
The ADP3153’s linear regulator controller drives an external
N-channel device. The output voltage is set by the ratio of the
external feedback resistors. The controller has been designed for
excellent load transient response.
VCC
+12V
VIN
+5V
VO2
+3.3V
1A
R1
VIN
+5V R2
IRL2703
1000F
35k
20k
22F 1F
CCOMP
SD VCC
DRIVE1
CMP
ADP3153
VLDO
SENSE+
SENSE–
IRL3103
1nF
150pF
FB DRIVE2
CT PGND
AGND
VID0–VID4
IRL3103
+ CIN
L
2.5H
RSENSE
7m
10BQ015
+ CO
VO
1.8V–3.5V
14A
5-BIT CODE
Figure 1. Typical Application
Pentium is a registered trademark of Intel Corporation.
All other trademarks are the property of their respective holders.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998




ADP3153 pdf, 반도체, 판매, 대치품
ADP3153
100k
P
SYSTEM
VO2 1
+3.3V
1A
2
RTN
IRL2703
1000F
RPROG
35k
R3
20k
22
ADP3153
1 VID1
VID0 20
2 VID2
PGND 19
3 VID3
NC 18
4 VID4
DRIVE1 17
5 AGND
DRIVE2 16
6 SD
VCC 15
7 FB
PWRGD 14
8 NC
CMP 13
9 VLDO
CT 12
10 SENSE– SENSE+ 11
NC = NO CONNECT
22F
1F
IRL3103
R1
150k
IRL3103
R2
39k
2nF
CCOMP
CT
150pF
220
1nF 220
2700F ؋3
(10V)
L2
1.7H
1F
L1
2.5H
RSENSE
6.7m
2700F ؋6
(10V)
10BQ015
Figure 2. Typical VRM8.2 Compliant Core DC/DC Converter Circuit
VIN +12V
VCC +5V
+5V RTN
+12V RTN
VO
1.8V–3.5V
0-14A
RTN
SD 6
VCC DRIVE1 DRIVE2 PGND AGND PWRGD SENSE+ SENSE–
15
5 14
11 10
ADP3153
NONOVERLAP
DRIVE
CROWBAR
IN
OFF
VREF +15%
DELAY
VREF +5% VREF –5%
CMPI
REFERENCE
2R
1.20V
S
Q
R
VT2
VT1
gm VREF
R
CMPT OFF-TIME
CONTROL
VIN
SENSE–
12 13
CT CMP
DAC
Figure 3. Functional Block Diagram
9 VLDO
FB
VID0
1 VID1
2 VID2
3 VID3
4 VID4
–4– REV. 0

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ADP3153 전자부품, 판매, 대치품
ADP3153
1.0 V, the crowbar will release, allowing the output voltage to
recover to 2.0 V.
Shutdown
The ADP3153 has a shutdown pin which is pulled logic low by
an internal resistor. In this condition the device functions nor-
mally. This pin should be pulled high externally to disable the
output drives.
Calculation of Component Values
The design parameters for a typical 300 MHz Pentium II appli-
cation (Figure 2) are as follows:
Input voltage: VIN = 5 V
Auxiliary input: VCC = 12 V
Output voltage: VO = 2.8 V
Maximum output current:
IOMAX = 14.2 Adc
Minimum output current:
IOMIN = 0.8 Adc
Static tolerance of the supply voltage for the processor core:
VOST+ = 100 mV
VOST– = –60 mV
Transient tolerance (for less than 2 µs) of the supply voltage for
the processor core when the load changes between the minimum
and maximum values with a di/dt of 30 A/µs:
VOTR+ = 130 mV
VOTR– = –130 mV
Input current di/dt when the load changes between the mini-
mum and maximum values: less than 0.1 A/µs
The above requirements correspond to Intel’s published power
supply requirements based on VRM 8.2 guidelines.
CT Selection for Operating Frequency
The ADP3153 uses a constant-off-time architecture with tOFF
determined by an external timing capacitor CT. Each time the
high side N-channel MOSFET switch turns on, the voltage
across CT is reset to approximately 3.3 V. During the off time,
CT is discharged by a constant current of 65 µA to 2.3 V, that is
by 1 V. The value of the off time is calculated from the pre-
ferred continuous-mode operating frequency. Assuming a nomi-
nal operating frequency of fNOM = 200 kHz at an output voltage
of VO = 2.8 V, the corresponding off time is:
tOFF
=
1
VO
V IN

1
f NOM
= 2.2 µs
The timing capacitor can be calculated from the equation:
CT
= tOFF
× 65 µA = 143
1V
pF
The converter operates at the nominal operating frequency only
at the above specified VO and at light load. At higher VO, and
heavy load, the operating frequency decreases due to the para-
sitic voltage drops across the power devices. The actual mini-
mum frequency at VO = 2.8 V is calculated to be 160 kHz (see
Equation 1 below), where:
IIN
RIN
RDS(ON)HSF
RDS(ON)LSF
RSENSE
RL
is the input dc current (assuming an efficiency
of 90%, IIN = 9 A)
is the resistance of the input filter (estimated
value: 7 m)
is the resistance of the high side MOSFET
(estimated value: 10 m)
is the resistance of the low side MOSFET
(estimated value: 10 m)
is the resistance of the sense resistor
(estimated value: 7 m)
is the resistance of the inductor (estimated
value: 6 m)
CO Selection—Determining the ESR
The selection of the output capacitor is driven by the required
ESR and capacitance CO. The ESR must be small enough that
both the resistive voltage deviation due to a step change in the
load current and the output ripple voltage stay below the values
defined in the specification of the supplied microprocessor. The
capacitance, CO, must be large enough that the output is held
up while the inductor current ramps up or down to the value
corresponding to the new load current.
The total static tolerance of the Pentium II processor is 160 mV.
Taking into account the ±1% setpoint accuracy of the ADP3153,
and assuming a 0.5% (or 14 mV) peak-to-peak ripple, the al-
lowed static voltage deviation of the output voltage when the
load changes between the minimum and maximum values is
0.08 V. Assuming a step change of I = IOMAX – IOMIN = 13.4 A,
and allocating all of the total allowed static deviation to the
contribution of the ESR sets the following limit:
RE(MAX ) = ESRMAX1 = 0.08 = 5.9 m
13. 4
The output filter capacitor must have an ESR of less than
5.9 m. One can use, for example, six FA type capacitors from
Panasonic, with 2700 µF capacitance, 10 V voltage rating, and
34 mESR. The six capacitors have a total typical ESR of
~ 5 mwhen connected in parallel.
Inductor Selection
The minimum inductor value can be calculated from ESR, off
time, dc output voltage and allowed peak-to-peak ripple voltage.
LMIN1 = VOtOFF RE(MAX ) = 2.8 × 2.2 µ × 5.9 m = 2.6 µH
V RIPPLE , p p
14 m
The minimum inductance gives a peak-to-peak ripple current of
2.15 A, or 15% of the maximum dc output current IOMAX.
f MIN
=1
tOFF
× V IN IIN RIN IOMAX (RDS(ON )HSF + RSENSE + RL ) –VO
= 160
V IN IIN RIN IOMAX (RDS(ON )HSF + RSENSE + RL RDS(ON )LSF )
kHz
(1)
REV. 0
–7–

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