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PDF ADP3156 Data sheet ( Hoja de datos )
| Número de pieza | ADP3156 | |
| Descripción | Dual Power Supply Controller for Desktop Systems | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Dual Power Supply Controller
for Desktop Systems
ADP3156
FEATURES
Active Voltage Positioning with Gain and Offset
Adjustment
Optimal Compensation for Superior Load Transient
Response
Fixed 1.5 V, 1.8 V and 2.5 V Output Versions
Dual N-Channel Synchronous Driver
On-Board Linear Regulator Controller
Total Output Accuracy ؎1% Over Temperature
High Efficiency, Current-Mode Operation
Short Circuit Protection
Overvoltage Protection Crowbar Protects Loads with
No Additional External Components
Power Good Output
SO-16 Package
APPLICATIONS
Desktop Computer Supplies
ACPI-Compliant Power Systems
General Purpose DC-DC Converters
GENERAL DESCRIPTION
The ADP3156 is a highly efficient synchronous buck switching
regulator controller optimized for converting the 3.3 V or 5 V
main supply into lower supply voltages required on the mother-
boards of Pentium® III and other high performance processor
systems. The ADP3156 uses a current mode, constant off-time
architecture to drive two external N-channel MOSFETs at a
programmable switching frequency that can be optimized for
size and efficiency. It also uses a unique supplemental regulation
technique called active voltage positioning to enhance load
transient performance. Active voltage positioning results in a
DC/DC converter that provides the best possible transient re-
sponse using the minimum number of output capacitors and
smallest footprint. Unlike voltage-mode and standard current-
mode architectures, active voltage positioning adjusts the output
voltage as a function of the load current so that it is always
optimally positioned for a system transient.
The ADP3156 provides accurate and reliable short circuit
protection and adjustable current limiting. It also includes an
integrated overvoltage crowbar function to protect the micro-
processor from destruction in case the core supply exceeds the
nominal programmed voltage by more than 15%.
FUNCTIONAL BLOCK DIAGRAM
VCC DRIVE1 DRIVE2 PGND AGND PWRGD SENSE+ SENSE–
DELAY
NONOVERLAP
SD
DRIVE
VREF +15%
CROWBAR
IN OFF
CMPI
VREF +5% VREF –5%
2R
S
Q
R
VT2
VT1
VREF
gm
R
REFERENCE
CT CMPT
OFF-TIME VIN
CONTROL SENSE–
1.20V
ADP3156
VLDO
FB
CMP
The ADP3156 contains a linear regulator controller that is
designed to drive an external N-channel MOSFET. This linear
regulator is used to generate the auxiliary voltages (AGP, GTL,
etc.) required in most motherboard designs, and has been de-
signed to provide a high bandwidth load-transient response. A
pair of external feedback resistors sets the linear regulator out-
put voltage.
VO2
1000F
VCC +12V
22F 1F
R1
35k⍀
20k⍀
R2
SD VCC
DRIVE1
VLDO
ADP3156
CCOMP
200pF
SENSE+
FB
CMP SENSE–
DRIVE2
CT
AGND PGND
VIN +5V
CIN
+
L RSENSE
VO
+
1nF CO
Figure 1. Typical Application
Pentium is a registered trademark of Intel Corporation.
All other trademarks are the property of their respective holders.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
1 page  
100
95 VOUT = 2.5V
VOUT = 1.8V
90
85
VOUT = 1.5V
80
75
0.5
SEE FIGURE 2
1.5 2.5 3.5 4.5 5.5 6.5
OUTPUT CURRENT – Amps
Figure 4. Efficiency vs. Output
Current
Typical Performance Characteristics–ADP3156
450
400
350
300
250
200
150
100
50
0
50 100 200 300 400 500 600 700 800
TIMING CAPACITOR – pF
Figure 5. Frequency vs. Timing
Capacitor
45
40
35
30
25
20
15
10
5
0
45
QGATE(TOTAL) = 100nC
58 83 134
OPERATING FREQUENCY – kHz
397
Figure 6. Supply Current vs.
Operating Frequency
SEE FIGURE 2
IOUT = 10A
PRIMARY
N-DRIVE
DRIVER OUTPUT
1
SECONDARY
N-DRIVE
DRIVER OUTPUT
2
DRIVE 1 AND 2 = 5V/DIV
500ns/DIV
Figure 7. Gate Switching Waveforms
SEE FIGURE 2
VCC = +12V
VIN = +5V
IOUT = 10A
100ns/DIV
Figure 8. Driver Transition
Waveforms
OUTPUT VOLTAGE
50mV/DIV
OUTPUT CURRENT
7A TO 1A
10s/DIV
Figure 9. Transient Response,
7 A–1 A of Figure 2 Circuit
OUTPUT VOLTAGE
50mV/DIV
OUTPUT CURRENT
1A TO 7A
10s/DIV
Figure 10. Transient Response,
1 A–7 A of Figure 2 Circuit
VCC VOLTAGE
5V/DIV
3
REGULATOR
OUTPUT VOLTAGE
1V/DIV
4
10ms/DIV
Figure 11. Power-On Start-Up
Waveforms
REV. 0
–5–
5 Page 
ADP3156
Efficiency of the Linear Regulator
The efficiency and corresponding power dissipation of the linear
regulator are not determined by the ADP3156. Rather, these are
a function of input and output voltage and load current. Effi-
ciency is approximated by the formula:
η = 100% × (VOUT Ϭ VIN)
The corresponding power dissipation in the MOSFET, together
with any resistance added in series from input to output is given
by:
×PLDO = (VIN(LDO) – VOUT(LDO)) IOUT(LDO)
Minimum power dissipation and maximum efficiency are ac-
complished by choosing the lowest available input voltage that
exceeds the desired output voltage. However, if the chosen
input source is itself generated by a linear regulator, its power
dissipation will be increased in proportion to the additional
current it must now provide. For most PC systems, the lowest
available input source for the linear regulators, which is not
itself generated by a linear regulator, is 3.3 V from the main
power supply. However, in this case, the main output of the
ADP3156 creates a lower voltage that may be used as the source
supply for the linear regulator. Assuming that a 1.8 V main
output is used to provide power for a 1.5 V linear regulator
output, the efficiency will nominally be 1.5 V ÷ 1.8 V = 83%.
If the 1.5 V output must supply a 4 A maximum load (a total of
6 W), the steady state dissipation in the MOSFET may be as
high as:
PLDO(MAX) = (VIN – VOUT) × IOUT(MAX) = (1.8 V – 1.5 V) × 4 A
= 1.2 W
The minimum acceptable on resistance of the MOSFET that
would deliver the 4 A load with only a 0.3 V difference between
input and output is:
RDS(ON, MAX) = (VOUT – VIN) ÷ IOUT(MAX) = (1.8 V – 1.5 V) ÷ 4 A
= 75 mΩ
There are many MOSFETs to choose from that can support the
maximum power dissipation without need for a heat sink and
without exceeding the calculated maximum on-resistance. For
simplicity it may be desirable to use the same MOSFET as is
used for the main power converter.
The output voltage may be programmed by the RPROG resistor
as follows:
RPROG
=
VO2
1.2 V
– 1
×
20
kΩ
=
1.5
1.2
−
1
×
20
kΩ
=
5
kΩ
The output filter capacitor maximum allowed ESR is:
ESR~VTR2/IOMAX = 0.036/0.5 = 0.072 Ω
where VTR2 is the maximum allowed transient deviation on the
output. This requirement is met using a 1000 µF/10 V LXV
series capacitor from United Chemicon. For applications requir-
ing higher output current, a heat sink and/or a larger MOSFET
should be used to reduce the MOSFET’s junction-to-ambient
thermal impedance.
LAYOUT AND COMPONENT PLACEMENT GUIDELINES
The following guidelines are recommended for optimal perfor-
mance of a switching regulator in a PC system:
General Recommendations
1. For best results, a four-layer (minimum) PCB is recom-
mended. This should allow the needed versatility for control
circuitry interconnections with optimal placement, a signal
ground plane, power planes for both power ground and the
input power (e.g., 5 V), and wide interconnection traces in
the rest of the power delivery current paths. Each square
unit of 1 ounce copper trace has a resistance of ~0.53 mΩ at
room temperature.
2. Whenever high currents must be routed between PCB layers
vias should be used liberally to create several parallel current
paths so that the resistance and inductance introduced by
these current paths is minimized and the via current rating is
not exceeded.
3. The power and ground planes should overlap each other as
little as possible. It is generally the easiest (although not
necessary) to have the power and signal ground planes on
the same PCB layer. The planes should be connected near-
est to the first input capacitor where the input ground cur-
rent flows from the converter back to the power source (e.g.,
5 V).
4. If critical signal lines (including the voltage and current
sense lines of the ADP3156) must cross through power
circuitry, it is best if a signal ground plane can be interposed
between those signal lines and the traces of the power cir-
cuitry. This serves as a shield to minimize noise injection
into the signals at the expense of making signal ground a bit
noisier.
5. The PGND pin of the ADP3156 should connect first to a
ceramic bypass capacitor (on the VCC pin) and then into the
power ground plane using the shortest possible trace. How-
ever, the power ground plane should not extend under other
signal components, including the ADP3156 itself. If neces-
sary, follow the preceding guideline to use the signal plane
as a shield between the power ground plane and the signal
circuitry.
6. The AGND pin of the ADP3156 should connect first to the
timing capacitor (on the CT pin), and then into the signal
ground plane. In cases where no signal ground plane can be
used, short interconnections to other signal ground circuitry
in the power converter should be used—the compensation
capacitor being the next most critical.
7. The output capacitors of the power converter should be
connected to the signal ground plan even though power
current flows in the ground of these capacitors. For this
reason, it is advised to avoid critical ground connections (e.g.,
the signal circuitry of the power converter) in the signal ground
plane in between the input and output capacitors. It is also
advised to keep the planar interconnection path short (i.e.,
have input and output capacitors close together).
8. The output capacitors should also be connected as closely as
possible to the load (or connector) which receives the power
(e.g., a microprocessor core). If the load is distributed, the
capacitors also should be distributed, and generally in pro-
portion to where the load tends to be more dynamic.
REV. 0
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ADP3156.PDF ] | |
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