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부품번호 ADP3157 기능
기능 5-Bit Programmable Synchronous Controller for Pentium III Processors
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ADP3157 데이터시트, 핀배열, 회로
a
5-Bit Programmable Synchronous
Controller for Pentium® III Processors
ADP3157
FEATURES
Active Voltage Positioning with Gain and Offset
Adjustment
Optimal Compensation for Superior Load Transient
Response
VRM 8.2, VRM 8.3 and VRM 8.4 Compliant
5-Bit Digitally Programmable 1.3 V to 3.5 V Output
Dual N-Channel Synchronous Driver
Total Output Accuracy ؎1% Over Temperature
High Efficiency, Current-Mode Operation
Short Circuit Protection
Overvoltage Protection Crowbar Protects Microprocessors
with No Additional External Components
Power Good Output
SO-16 Package
APPLICATIONS
Desktop PC Power Supplies for:
Pentium II and Pentium III Processor Families
AMD-K6 Processors
VRM Modules
GENERAL DESCRIPTION
The ADP3157 is a highly efficient synchronous buck switching
regulator controller optimized for converting the 5 V main sup-
ply into the core supply voltage required by the Pentium III and
other high performance processors. The ADP3157 uses an
internal 5-bit DAC to read a voltage identification (VID) code
directly from the processor, which is used to set the output
voltage between 1.3 V and 3.5 V. The ADP3157 uses a current
mode, constant off-time architecture to drive two external N-
channel MOSFETs at a programmable switching frequency that
can be optimized for size and efficiency. It also uses a unique
supplemental regulation technique called active voltage position-
ing to enhance load transient performance.
Active voltage positioning results in a dc/dc converter that meets
the stringent output voltage specifications for Pentium II and
Pentium III processors, with the minimum number of output
capacitors and smallest footprint. Unlike voltage-mode and
standard current-mode architectures, active voltage positioning
adjusts the output voltage as a function of the load current so that
it is always optimally positioned for a system transient.
The ADP3157 provides accurate and reliable short circuit pro-
tection and adjustable current limiting. It also includes an
integrated overvoltage crowbar function to protect the micro-
processor from destruction in case the core supply exceeds the
nominal programmed voltage by more than 15%.
FUNCTIONAL BLOCK DIAGRAM
VCC DRIVE1 DRIVE2 PGND AGND PWRGD SENSE+ SENSE–
DELAY
NONOVERLAP
SD
DRIVE
VREF +15%
CROWBAR
2R
IN
VREF +5% VREF –5%
CMPI
S
Q
R
VT1
VREF
R
VT2
gm
REFERENCE
CT CMPT
OFF-TIME
CONTROL
SENSE –
ADP3157
1.20V
DAC
VID0
VID1
VID2
VID3
VID4
CMP
VCC +12V
VIN +5V
22F 1F
VCC
CIN
+
SD DRIVE1
R1
ADP3157
L RSENSE
VO
1.3V TO
SENSE+
CMP
1nF
+ 3.5V
CO
R2 CCOMP
SENSE–
150pF
CT DRIVE2
AGND PGND
VID0–VID4
5-BIT CODE
Figure 1. 5-Bit Code Typical Application
Pentium is a registered trademark of Intel Corporation.
All other trademarks are the property of their respective holders.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999




ADP3157 pdf, 반도체, 판매, 대치품
ADP3157
100k
P
SYSTEM
22
ADP3157
1 VID1
VID0 16
2 VID2
PGND 15
3 VID3
DRIVE1 14
4 VID4
DRIVE2 13
5 AGND
6 SD
VCC 12
PWRGD 11
7 SENSE–
CMP 10
8 SENSE+
CT 9
22F
1F
IRL3803
R1
105k
IRL3803
R2
18.2k
CCOMP
3600pF
CT
200pF
220
1nF 220
ESR = 25mEACH
2200F ؋3
(25V)
L2
1H
1F
L1
1.7H
RSENSE
5m
ESR = 25mEACH
2200F ؋6
(25V)
10BQ015
Figure 2. Typical VRM8.2/8.3/8.4 Compliant Core DC/DC Converter Circuit
VCC +12V
VIN +5V
+5V RTN
+12V RTN
VO
1.3V TO
3.5V
0-19A
RTN
VCC DRIVE1 DRIVE2 PGND AGND PWRGD SENSE+ SENSE–
12 14
13
5 11
SD 6
CT
NONOVERLAP
DRIVE
CROWBAR
IN
S
Q
R
VT2
CMPT
VREF +15%
DELAY
VREF +5% VREF –5%
CMPI
VT1
gm
OFF-TIME
CONTROL
SENSE–
ADP3157
2R REFERENCE
1.20V
VREF
R
DAC
VID0
1 VID1
2 VID2
3 VID3
4 VID4
10
CMP
Figure 3. Functional Block Diagram
–4– REV. A

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ADP3157 전자부품, 판매, 대치품
ADP3157
Power Good
The ADP3157 has an internal monitor that senses the output
voltage and drives the PWRGD pin of the device. This pin is an
open drain output whose high level (when connected to a pull-
up resistor) indicates that the output voltage has been within a
± 5% regulation band of the targeted value for more than 500 µs.
The PWRGD pin will go low if the output is outside the regula-
tion band for more than 500 µs.
Output Crowbar
An added feature of using an N-channel MOSFET as the syn-
chronous switch is the ability to crowbar the output with the
same MOSFET. If the output voltage is 15% greater than the
targeted value, the ADP3157 will turn on the lower MOSFET,
which will current-limit the source power supply or blow its
fuse, pull down the output voltage, and thus save the micropro-
cessor from destruction. The crowbar function releases at ap-
proximately 50% of the nominal output voltage. For example, if
the output is programmed to 2.0 V, but is pulled up to 2.3 V or
above, the crowbar will turn on the lower MOSFET. If in this
case the output is pulled down to less than 1.0 V, the crowbar
will release, allowing the output voltage to recover to 2.0 V if
the fault condition has been removed.
Shutdown
The ADP3157 has a shutdown (SD) pin that is pulled down by
an internal resistor. In this condition the device functions nor-
mally. This pin should be pulled high to disable the output drives.
APPLICATION INFORMATION
Specifications for a Design Example
The design parameters for a typical 550 MHz Pentium III appli-
cation (Figure 2) are as follows:
Input voltage: VIN = 5 V
Auxiliary input: VCC = 12 V
Output voltage: VO = 2.0 V
Maximum output current:
IOMAX = 17.0 A dc
Minimum output current:
IOMIN = 1.0 A dc
Static tolerance of the supply voltage for the processor core:
VOST+ = +70 mV
VOST– = –70 mV
Transient tolerance (for less than 2 µs) of the supply voltage for
the processor core when the load changes between the minimum
and maximum values with a di/dt of 30 A/µs:
VOTR+ = +140 mV
VOTR– = –140 mV
Input current di/dt when the load changes between the mini-
mum and maximum values: less than 8 A/µs
The above requirements correspond to Intel’s published power
supply requirements based on Intel Pentium III specifications.
CT Selection for Operating Frequency
The ADP3157 uses a constant-off-time architecture with tOFF
determined by an external timing capacitor CT. Each time the
high side N-channel MOSFET switch turns on, the voltage
across CT is reset to approximately 3.3 V. During the off time,
CT is discharged by a constant current of 65 µA. Once CT
reaches 2.3 V, a new on-time cycle is initiated. The value of the
off-time is calculated using the continuous-mode operating
frequency. Assuming a nominal operating frequency of fNOM =
200 kHz at an output voltage of 2.0 V, the corresponding off
time is:
tOFF
=
1
VO
VIN

1
fNOM
=
3.0
µs
The timing capacitor can be calculated from the equation:
CT
=
tOFF
× 65 µA =
1V
200
pF
The converter operates at the nominal operating frequency only
at the above specified VOUT and at light load. At higher VOUT or
heavy load, the operating frequency decreases due to the para-
sitic voltage drops across the power devices. The actual mini-
mum frequency at VOUT = 2.0 V is calculated to be 180 kHz (see
Equation 1), where:
IIN
RIN
RDS(ON)HSF
is the input dc current
(assuming an efficiency of 90%, IIN = 7.5 A)
is the resistance of the input filter
(estimated value: 7 m)
is the resistance of the high side MOSFET
(estimated value: 10 m)
RDS(ON)LSF
RSENSE
RL
is the resistance of the low side MOSFET
(estimated value: 10 m)
is the resistance of the sense resistor
(estimated value: 5 m)
is the resistance of the inductor
(estimated value: 6 m)
COUT Selection–Determining the ESR
The required ESR and capacitance drive the selection of the
type and quantity of the output capacitors. The ESR must be
small enough that both the resistive voltage deviation due to a
step change in the load current and the output ripple voltage
stay below the values defined in the specification of the supplied
microprocessor. The capacitance must be large enough that the
output is held up while the inductor current ramps up or down
to the value corresponding to the new load current.
The total static tolerance of the Pentium III processor is 140 mV.
Taking into account the ±1% setpoint accuracy of the ADP3157,
and assuming a 0.5% (or 10 mV) peak-to-peak ripple, the al-
lowed static voltage deviation of the output voltage when the
load changes between the minimum and maximum values is
90 mV. Assuming a step change of I = IOMAX–IOMIN = 16 A,
and allocating all of the total allowed static deviation to the
contribution of the ESR sets the following limit:
RE(MAX )
=
ESRMAX1
= 90 mV
16 A
= 5.6 m
The output filter capacitor must have an ESR of less than 5.6 m.
One can use, for example, two SP-Type OS-CON capacitors
from Sanyo, with 2200 µF capacitance, 7 V voltage rating, and
f MIN
=
1
tOFF
× VIN IIN RIN IOMAX(RDS(ON )HSF + RSENSE + RL ) – VO
= 180 kHz
VIN IIN RIN IOMAX(RDS(ON )HSF + RSENSE + RL RDS(ON )LSF )
(1)
REV. A
–7–

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