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PDF ADP3157JR Data sheet ( Hoja de datos )
| Número de pieza | ADP3157JR | |
| Descripción | 5-Bit Programmable Synchronous Controller for Pentium III Processors | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
5-Bit Programmable Synchronous
Controller for Pentium® III Processors
ADP3157
FEATURES
Active Voltage Positioning with Gain and Offset
Adjustment
Optimal Compensation for Superior Load Transient
Response
VRM 8.2, VRM 8.3 and VRM 8.4 Compliant
5-Bit Digitally Programmable 1.3 V to 3.5 V Output
Dual N-Channel Synchronous Driver
Total Output Accuracy ؎1% Over Temperature
High Efficiency, Current-Mode Operation
Short Circuit Protection
Overvoltage Protection Crowbar Protects Microprocessors
with No Additional External Components
Power Good Output
SO-16 Package
APPLICATIONS
Desktop PC Power Supplies for:
Pentium II and Pentium III Processor Families
AMD-K6 Processors
VRM Modules
GENERAL DESCRIPTION
The ADP3157 is a highly efficient synchronous buck switching
regulator controller optimized for converting the 5 V main sup-
ply into the core supply voltage required by the Pentium III and
other high performance processors. The ADP3157 uses an
internal 5-bit DAC to read a voltage identification (VID) code
directly from the processor, which is used to set the output
voltage between 1.3 V and 3.5 V. The ADP3157 uses a current
mode, constant off-time architecture to drive two external N-
channel MOSFETs at a programmable switching frequency that
can be optimized for size and efficiency. It also uses a unique
supplemental regulation technique called active voltage position-
ing to enhance load transient performance.
Active voltage positioning results in a dc/dc converter that meets
the stringent output voltage specifications for Pentium II and
Pentium III processors, with the minimum number of output
capacitors and smallest footprint. Unlike voltage-mode and
standard current-mode architectures, active voltage positioning
adjusts the output voltage as a function of the load current so that
it is always optimally positioned for a system transient.
The ADP3157 provides accurate and reliable short circuit pro-
tection and adjustable current limiting. It also includes an
integrated overvoltage crowbar function to protect the micro-
processor from destruction in case the core supply exceeds the
nominal programmed voltage by more than 15%.
FUNCTIONAL BLOCK DIAGRAM
VCC DRIVE1 DRIVE2 PGND AGND PWRGD SENSE+ SENSE–
DELAY
NONOVERLAP
SD
DRIVE
VREF +15%
CROWBAR
2R
IN
VREF +5% VREF –5%
CMPI
S
Q
R
VT1
VREF
R
VT2
gm
REFERENCE
CT CMPT
OFF-TIME
CONTROL
SENSE –
ADP3157
1.20V
DAC
VID0
VID1
VID2
VID3
VID4
CMP
VCC +12V
VIN +5V
22F 1F
VCC
CIN
+
SD DRIVE1
R1
ADP3157
L RSENSE
VO
1.3V TO
SENSE+
CMP
1nF
+ 3.5V
CO
R2 CCOMP
SENSE–
150pF
CT DRIVE2
AGND PGND
VID0–VID4
5-BIT CODE
Figure 1. 5-Bit Code Typical Application
Pentium is a registered trademark of Intel Corporation.
All other trademarks are the property of their respective holders.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
1 page  
100
VOUT = 3.5V
95 VOUT = 2.8V
90
85
VOUT = 2.0V
80 VOUT = 1.3V
75
70
SEE FIGURE 2
65
1.4 2.8 4.2 5.6 7 8.4 9.8 11.2 12.6 14
OUTPUT CURRENT – Amps
Figure 4. Efficiency vs. Output
Current
Typical Performance Characteristics–ADP3157
450
400
350
300
250
200
150
100
50
0
50 100 200 300 400 500 600 700 800
TIMING CAPACITOR – pF
Figure 5. Frequency vs. Timing
Capacitor
45
40
35
30
25
20
15
10
5
0
45
QGATE(TOTAL) = 100nC
58 83 134
OPERATING FREQUENCY – kHz
397
Figure 6. Supply Current vs. Oper-
ating Frequency
SEE FIGURE 2
PRIMARY
N-DRIVE
DRIVER OUTPUT
1
SECONDARY
N-DRIVE
DRIVER OUTPUT
2
DRIVE 1 AND 2 = 5V/DIV
500ns/DIV
Figure 7. Gate Switching Waveforms
SEE FIGURE 2
VCC = +12V
VIN = +5V
IOUT = 10A
100ns/DIV
Figure 8. Driver Transition
Waveforms
OUTPUT VOLTAGE
20mV/DIV
OUTPUT CURRENT
1A TO 19A
10s/DIV
Figure 10. Load Transient Response,
1 A–19 A of Figure 2 Circuit
VCC VOLTAGE
5V/DIV
3
REGULATOR
OUTPUT VOLTAGE
1V/DIV
4
10ms/DIV
Figure 11. Power-On Start-Up
Waveform
OUTPUT VOLTAGE
20mV/DIV
OUTPUT CURRENT
19A TO 1A
10s/DIV
Figure 9. Load Transient Response,
19 A–1 A of Figure 2 Circuit
25
TA = +25؇C
SEE FIGURE 13
20
15
10
5
0
OUTPUT ACCURACY – %
Figure 12. Output Accuracy
Distribution, VOUT = 2.0 V
REV. A
–5–
5 Page 
ADP3157
4. If critical signal lines (including the voltage and current
sense lines of the ADP3157) must cross through power
circuitry, it is best if a signal ground plane can be inter-
posed between those signal lines and the traces of the
power circuitry. This serves as a shield to minimize noise
injection into the signals at the expense of making signal
ground a bit noisier.
5. The PGND pin of the ADP3157 should connect first to a
ceramic bypass capacitor (on the VCC pin) and then into the
power ground plane using the shortest possible trace. How-
ever, the power ground plane should not extend under
other signal components, including the ADP3157 itself. If
necessary, follow the preceding guideline to use the signal
plane as a shield between the power ground plane and the
signal circuitry.
6. The AGND pin of the ADP3157 should connect first to the
timing capacitor (on the CT pin), and then into the signal
ground plane. In cases where no signal ground plane can be
used, short interconnections to other signal ground cir-
cuitry in the power converter should be used—the compen-
sation capacitor being the next most critical.
7. The output capacitors of the power converter should be
connected to the signal ground plan even though power
current flows in the ground of these capacitors. For this
reason, it is advised to avoid critical ground connections (e.g.,
the signal circuitry of the power converter) in the signal
ground plane between the input and output capacitors. It
is also advised to keep the planar interconnection path short
(i.e., have input and output capacitors close together).
8. The output capacitors should also be connected as closely
as possible to the load (or connector) that receives the
power (e.g., a microprocessor core). If the load is distrib-
uted, the capacitors also should be distributed, and gen-
erally in proportion to where the load tends to be more
dynamic.
9. Absolutely avoid crossing any signal lines over the switching
power path loop, described below.
Power Circuitry
10. The switching power path should be routed on the PCB to
encompass the smallest possible area in order to minimize
radiated switching noise energy (i.e., EMI). Failure to take
proper precaution often results in EMI problems for the
entire PC system as well as noise related operational prob-
lems in the power converter control circuitry. The switching
power path is the loop formed by the current path through
the input capacitors, the two FETs, and the power Schottky
diode if used, including all interconnecting PCB traces and
planes. The use of short and wide interconnection traces is
especially critical in this path for two reasons: it minimizes
the inductance in the switching loop, which can cause high-
energy ringing, and it accommodates the high current de-
mand with minimal voltage loss.
11. A power Schottky diode (1 ~ 2 A dc rating) placed from the
lower FET’s source (anode) to drain (cathode) will help to
minimize switching power dissipation in the upper FET. In
the absence of an effective Schottky diode, this dissipation
occurs through the following sequence of switching events.
The lower FET turns off in advance of the upper FET
turning on (necessary to prevent cross-conduction). The
circulating current in the power converter, no longer find-
ing a path for current through the channel of the lower
FET, draws current through the inherent body-drain diode
of the FET. The upper FET turns on, and the reverse
recovery characteristic of the lower FET’s body-drain diode
prevents the drain voltage from being pulled high quickly.
The upper FET then conducts very large current while it
momentarily has a high voltage forced across it, which
translates into added power dissipation in the upper FET.
The Schottky diode minimizes this problem by carrying a
majority of the circulating current when the lower FET is
turned off, and by virtue of its essentially nonexistent re-
verse recovery time.
12. A small ferrite bead inductor placed in series with the drain
of the lower FET can also help to reduce this previously
described source of switching power loss.
13. Whenever a power dissipating component (e.g., a power
MOSFET) is soldered to a PCB, the liberal use of vias,
both directly on the mounting pad and immediately sur-
rounding it, is recommended. Two important reasons for
this are: improved current rating through the vias (if it is a
current path), and improved thermal performance—espe-
cially if the vias extended to the opposite side of the PCB
where a plane can more readily transfer the heat to the air.
14. The output power path, though not as critical as the switch-
ing power path, should also be routed to encompass a small
area. The output power path is formed by the current path
through the inductor, the current sensing resistor, the out-
put capacitors, and back to the input capacitors.
15. For best EMI containment, the power ground plane should
extend fully under all the power components except the
output capacitors. These are: the input capacitors, the
power MOSFETs and Schottky diode, the inductor, the
current sense resistor and any snubbing elements that
might be added to dampen ringing. Avoid extending the
power ground under any other circuitry or signal lines,
including the voltage and current sense lines.
Signal Circuitry
16. The output voltage is sensed and regulated between the
AGND pin (which connects to the signal ground plane)
and the SENSE– pin. The output current is sensed (as a
voltage) and regulated between the SENSE– pin and the
SENSE+ pin. In order to avoid differential mode noise
pickup in those sensed signals, their loop areas should be
small. Thus the SENSE– trace should be routed atop the
signal ground plane, and the SENSE+ and SENSE– traces
should be routed as a closely coupled pair (SENSE+ should
be over the signal ground plane as well).
17. The SENSE+ and SENSE– traces should be Kelvin con-
nected to the current sense resistor so that the additional
voltage drop due to current flow on the PCB at the current
sense resistor connections does not affect the sensed volt-
age. It is desirable to have the ADP3157 close to the output
capacitor bank and not in the output power path, so that
any voltage drop between the output capacitors and the
AGND pin is minimized, and voltage regulation is not
compromised.
REV. A
–11–
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| PDF Descargar | [ Datasheet ADP3157JR.PDF ] | |
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