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PDF ADP3164 Data sheet ( Hoja de datos )
| Número de pieza | ADP3164 | |
| Descripción | 5-Bit Programmable 4-Phase Synchronous Buck Controller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
ADOPT™ Optimal Positioning Technology for Superior
Load Transient Response and Fewest Output
Capacitors
Complies with VRM 9.1 with Lowest System Cost
4-Phase Operation at up to 500 kHz per Phase
Quad Logic-Level PWM Outputs for Interface to
External High-Power Drivers
Active Current Balancing between All Output Phases
Accurate Multiple VRM Module Current Sharing
5-Bit Digitally Programmable 1.1 V to 1.85 V Output
Total Output Accuracy ؎0.8% Over Temperature
Current-Mode Operation
Short Circuit Protection
Enhanced Power Good Output Detects Open Outputs
in Multi-VRM Power Systems
Overvoltage Protection Crowbar Protects
Microprocessors with No Additional
External Components
APPLICATIONS
Desktop PC Power Supplies for:
Intel Pentium® 4 Processors
VRM Modules
5-Bit Programmable 4-Phase
Synchronous Buck Controller
ADP3164
REF
GND
CT
FUNCTIONAL BLOCK DIAGRAM
VCC
UVLO
& BIAS
ADP3164
SET
RESET
CROWBAR
3.0V
REFERENCE
4-PHASE
DRIVER
LOGIC
OSCILLATOR
DAC + 20%
POWER
GOOD
PWM1
PWM2
PWM3
PWM4
PGND
PWRGD
SHARE
COMP
SOFT
START
CMP
CMP
DAC – 20%
VID
DAC
gm
CS–
CS+
FB
VID4 VID3 VID2 VID1 VID0
GENERAL DESCRIPTION
The ADP3164 is a highly efficient 4-phase synchronous buck
switching regulator controller optimized for converting a 12 V
main supply into the core supply voltage required by high per-
formance Intel processors. The ADP3164 uses an internal 5-bit
DAC to read a voltage identification (VID) code directly from
the processor, which is used to set the output voltage between
1.1 V and 1.85 V. The ADP3164 uses a current mode PWM
architecture to drive the logic-level outputs at a programmable
switching frequency that can be optimized for VRM size and
efficiency. The four output phases share the dc output current
to reduce overall output voltage ripple. An active current bal-
ancing function ensures that all phases carry equal portions of
the total load current, even under large transient loads, to mini-
mize the size of the inductors.
The ADP3164 also uses a unique supplemental regulation tech-
nique called active voltage positioning (ADOPT) to enhance
load transient performance. Active voltage positioning results in
a dc/dc converter that meets the stringent output voltage specifi-
cations for high-performance processors, with the minimum
number of output capacitors and smallest footprint. Unlike
voltage-mode and standard current-mode architectures, active
voltage positioning adjusts the output voltage as a function of the
load current so that it is always optimally positioned for a system
transient. The ADP3164 also provides accurate and reliable short
circuit protection, adjustable current limiting, and an enhanced
Power Good output that can detect open outputs in any phase for
single or multi-VRM systems.
The ADP3164 is specified over the commercial temperature
range of 0°C to 70°C and is available in a 20-lead TSSOP package.
ADOPT is a trademark of Analog Devices, Inc.
Pentium is a registered trademark of Intel Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
1 page  
Typical Performance Characteristics–ADP3164
10 25
TA = 25؇C
VOUT = 1.6V
20
15
1
10
5
0.1
0
50 100 150 200 250 300
CT CAPACITANCE – pF
TPC 1. Oscillator Frequency vs. Timing Capacitor (CT)
0
–0.5 0
OUTPUT ACCURACY – % of Nominal
TPC 3. Output Accuracy Distribution
0.5
4.5
4.4
4.3
4.2
4.1
4.0
0
500
1000
1500
2000
2500
OSCILLATOR FREQUENCY – kHz
3000
TPC 2. Supply Current vs. Oscillator Frequency
REV. 0
–5–
5 Page 
ADP3164
COUT Selection
The required equivalent series resistance (ESR) and capacitance
drive the selection of the type and quantity of the output capaci-
tors. The ESR must be less than or equal to the specified output
resistance (ROUT), in this case 0.95 mΩ. The capacitance must
be large enough that the voltage across the capacitors, which is
the sum of the resistive and capacitive voltage deviations, does
not deviate beyond the initial resistive step while the inductor
current ramps up or down to the value corresponding to the
new load current.
One can, for example, use thirteen SP-Type OS-CON capaci-
tors from Sanyo, with 820 µF capacitance, a 4 V voltage rating,
and 12 mΩ ESR. The ten capacitors have a maximum total ESR
of 0.92 mΩ when connected in parallel.
As long as the capacitance of the output capacitor bank is above
a critical value and the regulating loop is compensated with
Analog Devices’ proprietary compensation technique (ADOPT),
the actual capacitance value has no influence on the peak-to-
peak deviation of the output voltage to a full step change in the
load current. The critical capacitance can be calculated as follows:
COUT (CRIT ) =
IO
ROUT × VOUT
×L
n
=
80 A
× 600 nH = 8.56 mF
0.95 mΩ ×1.475V
4
(13)
The critical capacitance limit for this circuit is 8.56 mF, while
the actual capacitance of the thirteen OS-CON capacitors is
13 × 820 µF = 10.66 mF. In this case, the capacitance is safely
above the critical value.
Multilayer ceramic capacitors are also required for high-frequency
decoupling of the processor. The exact number of these MLC
capacitors is a function of the board layout space and parasitics.
Typical designs use twenty to thirty 10 µF MLC capacitors
located as close to the processor power pins as is practical.
Feedback Loop Compensation Design for ADOPT
Optimized compensation of the ADP3164 allows the best pos-
sible containment of the peak-to-peak output voltage deviation.
Any practical switching power converter is inherently limited by
the inductor in its output current slew rate to a value much less
than the slew rate of the load. Therefore, any sudden change of
load current will initially flow through the output capacitors,
and assuming that the capacitance of the output capacitor is
larger than the critical value defined by Equation 13, this will
produce a peak output voltage deviation equal to the ESR of the
output capacitor times the load current change.
The optimal implementation of voltage positioning, ADOPT,
will create an output impedance of the power converter that is
entirely resistive over the widest possible frequency range, includ-
ing dc, and equal to the maximum acceptable ESR of the output
capacitor array. With the resistive output impedance, the output
voltage will droop in proportion with the load current at any load
current slew rate; this ensures the optimal positioning and allows
the minimization of the output capacitor bank.
With an ideal current-mode-controlled converter, where the
average inductor current would respond without delay to the
command signal, the resistive output impedance could be
achieved by having a single-pole roll-off of the voltage gain of
the voltage-error amplifier. The pole frequency must coincide
with the ESR zero of the output capacitor bank. The ADP3164
uses constant frequency current-mode control, which is known
to have a nonideal, frequency-dependent command signal to
inductor current transfer function. The frequency dependence
manifests in the form of a pair of complex conjugate poles at
one-half of the switching frequency. A purely resistive output
impedance could be achieved by canceling the complex conjugate
poles with zeros at the same complex frequencies and adding a
third pole equal to the ESR zero of the output capacitor. Such a
compensating network would be quite complicated. Fortunately, in
practice it is sufficient to cancel the pair of complex conjugate
poles with a single real zero placed at one-half of the switching
frequency. Although the end result is not a perfectly resistive
output impedance, the remaining frequency dependence causes
only a small percentage of deviation from the ideal resistive
response. The single-pole and single-zero compensation can easily
be implemented by terminating the gm error amplifier with the
parallel combination of a resistor (RT) and a series RC network.
The value of the terminating resistor RT was previously deter-
mined; the capacitance and resistance of the series RC network
are calculated as follows:
COC
= COUT × ROUT
RT
−n
π × fOSC × RT
(14)
COC
=
10.7 mF × 0.92
7.48 kΩ
mΩ
−
π × 800
4
kHz × 7.48
kΩ
= 1.1 nF
The nearest standard value of COC is 1 nF. The resistance of the
zero-setting resistor in series with the compensating capacitor is:
RZ
=
n
π × fOSC × COC
=
4
π × 800 kHz ×1 nF
= 1.59 kΩ
(15)
The nearest standard 5% resistor value is 1.5 kΩ. Note that this
resistor is only required when COUT approaches CCRIT (within
25% or less). In this example, COUT is approaching CCRIT, so
RZ should be included.
Power MOSFETs
In this example, eight N-channel power MOSFETs must be used;
four as the main (control) switches, and the remaining four as
the synchronous rectifier switches. The main selection parameters
for the power MOSFETs are VGS(TH), QG and RDS(ON). The
minimum gate drive voltage (the supply voltage to the ADP3414)
dictates whether standard threshold or logic-level threshold
MOSFETs must be used. Since VGATE <8 V, logic-level thresh-
old MOSFETs (VGS(TH) < 2.5 V) are strongly recommended.
REV. 0
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADP3164.PDF ] | |
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