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PDF ADP3204JCP-REEL7 Data sheet ( Hoja de datos )
| Número de pieza | ADP3204JCP-REEL7 | |
| Descripción | 3-Phase IMVP-II and IMVP-III Core Controller for Mobile CPUs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
3-Phase IMVP-II and IMVP-III
Core Controller for Mobile CPUs
ADP3204*
FEATURES
Pin Selectable 1-, 2-, or 3-Phase Operation
Static and Dynamic Current Sharing Characteristics
Backward Compatible to IMVP-II
Superior Load Transient Response with ADOPT®
Analog Devices’ Optimal Positioning Technology
Noise-Blanking for Speed and Stability
Synchronous Rectifier Control Extends Battery Life
Smooth Output Transition During VID Code Change
Cycle-by-Cycle Current Limiting
Hiccup or Latched Overload Protection
Transient-Glitch-Free Power Good
Soft Start Eliminates Power-On In-Rush Current Surge
Two-Level Overvoltage and Reverse Voltage
Protection
APPLICATIONS
IMVP-II and IMVP-III Core DC-to-DC Converters
Fixed Voltage Mobile CPU Core DC-to-DC Converters
Notebook/Laptop Power Supplies
Programmable Output Power Supplies
GENERAL DESCRIPTION
The ADP3204 is a 1-, 2-, or 3-phase hysteretic peak current
dc-to-dc buck converter controller dedicated to power a mobile
processor’s core. The optimized low voltage design is powered
from the 3.3 V system supply. The nominal output voltage is
set by a 5-bit VID code. To accommodate the transition time
required by the newest processors, the ADP3204 features
high speed operation to allow a minimized inductor size that
results in the fastest change of current to the output. To
further allow for the minimum number of output capacitors
to be used, the ADP3204 features active voltage positioning
with ADOPT optimal compensation to ensure a superior
load transient response. The output signals interface with a
maximum of three ADP3415 MOSFET drivers that are
optimized for high speed and high efficiency for driving both the
top and bottom MOSFETs of the buck converter. The
ADP3204 is capable of controlling the synchronous rectifiers to
extend battery lifetime in light load conditions.
HYSSET
DSHIFT
BSHIFT
DPRSHIFT
FUNCTIONAL BLOCK DIAGRAM
ADP3204
BOM
DPSLP
DPRSLP
VCC
HYSTERESIS
SETTING
AND
SHIFT-MUX
VR
PHASE
SPLITTER
VID4
VID3
VID2
VID1
VID0
BOM
DPSLP
DPRSLP
PWRGD
SD
CLIM
EN
CORE
CURRENT
SENSE
MUX
DPRSLP
VID
GEN
VID
MUX
AND
REG
5-BIT VID
DAC
AND
FIXED
REF
VR
VID TRANSIENT
DETECTOR AND
SHIFT SELECTOR
COREGD MONITOR
SS-HICCUP TIMER
AND OCP
PWRGD BLANKER
SR CONTROL
ENABLE UVLO-MAIN BIAS OVP AND RVP
PM MODULE
GND
OUT3
OUT2
OUT1
CS3
CS2
CS1
CS+
CS–
RAMP
REG
DACOUT
DACRAMP
COREFB
SS
DRVLSD
CLAMP
ADOPT is a trademark of Analog Devices, Inc.
*Protected by U.S.Patent No. 5,969,657; other patents pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
1 page  
ADP3204
ABSOLUTE MAXIMUM RATINGS*
Input Supply Voltage (VCC) . . . . . . . . . . . . . . . –0.3 V to +7 V
All Other Inputs/Outputs . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Junction Temperature Range . . . . . . . . . . . . . . 0°C to +150°C
Junction to Air Thermal Resistance (θJA) . . . . . . . . . . . 98°C/W
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
ORDERING GUIDE
Model
Temperature
Range
Package
Package Quantity
Description Option per Reel
ADP3204JCP-REEL 0ºC to 100ºC
ADP3204JCP-REEL7 0ºC to 100ºC
LFCSP-32
LFCSP-32
CP-32
CP-32
5000
1500
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table I. VID CODE
VID3 VID2 VID1 VID0
0 00 0
0 00 1
0 01 0
0 01 1
0 10 0
0 10 1
0 11 0
0 11 1
1 00 0
1 00 1
1 01 0
1 01 1
1 10 0
1 10 1
1 11 0
1 11 1
0 00 0
0 00 1
0 01 0
0 01 1
0 10 0
0 10 1
0 11 0
0 11 1
1 00 0
1 00 1
1 01 0
1 01 1
1 10 0
1 10 1
1 11 0
1 11 1
VOUT
1.750
1.700
1.650
1.600
1.550
1.500
1.450
1.400
1.350
1.300
1.250
1.200
1.150
1.100
1.050
1.000
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
0.775
0.750
0.725
0.700
0.675
0.650
0.625
0.600
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADP3204 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. 0
–5–
5 Page 
110
OUT = HIGH, RHYS = 17k⍀
OUT = HIGH, RHYS = 170k⍀
0 OUT = LOW, RHYS = 170k⍀
–110
0
OUT = LOW, RHYS = 17k⍀
20 40 60
TEMPERATURE – ؇C
80
100
TPC 7. Core Hysteresis Current vs. Temperature
ADP3204
0
–50
–100
OUT = LOW, RHYSSET = 170k⍀
OUT = HIGH, RHYSSET = 170k⍀
–150
–200
–250
OUT = LOW, RHYSSET = 17k⍀
–300
–350
0
OUT = HIGH, RHYSSET = 17k⍀
20 40 60 80
AMBIENT TEMPERATURE – ؇C
100
TPC 8. Current Limit Threshold vs. Temperature
THEORY OF OPERATION
Overview
Featuring a new proprietary 1-, 2-, or 3-channel buck converter
hysteretic control architecture developed by Analog Devices, the
ADP3204 is the optimal core voltage control solution for both
IMVP-II and IMVP-III generation microprocessors. The complex
multitiered regulation requirements of either IMVP specifica-
tion are easily implemented with the highly integrated function-
ality of this controller.
Power Conversion Control Architecture
Driving of the individual channels is accomplished using external
drivers, such as the ADP3415. One PWM interface pin per
channel, OUT1, OUT2, and OUT3, is provided. A separate
pin, DRVLSD, commands the driver to enable or disable synchro-
nous rectifier operation during the off time of each channel. The
same DRVLSD pin is connected to all three drivers.
The ADP3204 utilizes hysteretic control. The resistor from
the HYSSET pin to ground sets up a current that is switched
bidirectionally into a resistor interconnected between the RAMP
and CS+ pins. The switching of this current sets the hysteresis.
In a multichannel configuration, the hysteretic control requires
multiplexing information in all channels. The inductor current
of the channel that is driven high is controlled against the upper
hysteresis limit. During the common offtime of the channels,
the inductor currents are averaged together and compared against
the lower hysteresis limit. This proprietary offtime averaging
technique serves to eliminate a systematic offset that otherwise
appears in a fully multiplexed hysteretic control system.
Compensation
As with all ADI products for core voltage control, the controller
is compatible with ADOPT compensation, which provides the
optimum output voltage containment within a specified voltage
window or along a specified load line using the fewest possible
output capacitors. The inductor ripple current is kept at a fixed
programmable value while the output voltage is regulated with
fully programmable voltage positioning parameters, which can
be tuned to optimize the design for any particular CPU regula-
tion specification. By controlling the ripple current rather than
the ripple voltage, the frequency variations associated with
changes in output impedance for standard ripple regulators will
not appear.
Feedback/Current Sensing
Accurate current sensing is needed to accomplish output voltage
positioning accurately, which, in turn, is required to allow the
minimum number of output capacitors to be used to contain
transients. A current sense resistor is used between each inductor
and the output capacitors. To allow the control to operate
without amplifiers, the negative feedback signal is multiplexed
from the inductor or upstream side of the current sense resistors,
and a positive feedback signal, if needed for load-line tuning, is
taken from the output or downstream side.
Output Voltage Programming by VID, Offsets, and Load Line
In the IMVP-II and IMVP-III specifications, the output voltage
is a function of both the core current (according to a specified
load line) and the system operating mode (i.e., performance or
battery optimized, normal or deep sleep clocking state, or deeper
sleep). The VID code programs the “nominal” core voltage.
The core voltage decreases as a function of load current along
the load line, which is synonymous with an output resistance of
the power converter. The core voltage is also offset by a dc
value—usually specified as a percentage—depending on the
operating mode. The voltage offset is also called a “shift.”
Two pins, BSHIFT and DSHIFT, are used to program the
magnitude of the voltage shifts. The voltage shifts are accom-
plished by injecting current at the node of the negative input pin
of the feedback comparator. Resistive termination at the pins
determines the magnitude of the voltage “shifts.”
Two other pins, BOM and DPSLP, are used to activate the
respective two shifts only in their active low states. In the
ADP3204, the shifts are mutually exclusive, with the Deep
Sleep shift (controlled by the DPSLP and DSHIFT pins) being
the dominant one. Another pin, DPRSLP, eliminates both
shifts only in its active high state. Its assertion corresponds to
the Deeper Sleep operating mode.
Current Limiting
The current programmed at the HYSSET pin and a resistor
from the CS– pin to the common node of the current sense
resistors set the current limit. If the current limit threshold is
triggered, a hysteresis is applied to the threshold so that hysteretic
control is maintained during a current limited operating mode.
REV. 0
–11–
11 Page | ||
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| PDF Descargar | [ Datasheet ADP3204JCP-REEL7.PDF ] | |
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