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PDF ADP3205 Data sheet ( Hoja de datos )
| Número de pieza | ADP3205 | |
| Descripción | Multiphase IMVP-IV Core Controller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Multiphase IMVP-IV
Core Controller for Mobile CPUs
ADP3205
FEATURES
Pin Programmable 1-, 2-, or 3-Phase Operation
Excellent Static and Dynamic Current Sharing
Superior Load Transient Response when Used with
ADOPT™ Optimal Positioning Technology
Noise-Blanking for Speed and Stability
Synchronous Rectification Control for Optimized Light
Load Efficiency
Soft DAC Output Voltage Transition for VID Change
Cycle-by-Cycle Current Limiting
Latched or Hiccup Current Overload Protection
Masked Power Good during Output Voltage Transients
Soft Start-Up without Power-On In-Rush Current Surge
2-Level Overvoltage and Reverse-Voltage Protection
APPLICATIONS
IMVP-IV CPU Core DC-to-DC Converters
Programmable Output Power Supplies
GENERAL DESCRIPTION
The ADP3205 is a 1-, 2-, or 3-phase hysteretic peak current mode
dc-to-dc buck converter controller dedicated to powering a mobile
processor’s core. The chip optimized low voltage design runs from
the 3.3 V system supply. The chip contains a precision 6-bit DAC
whose nominal output voltage is set by VID code. The ADP3205
features high speed operation to allow a minimized inductor size
that results in the fastest possible change of current to the output.
To further minimize the number of output capacitors, the con-
verter features active voltage positioning enhanced with ADOPT
optimal compensation to ensure a superior load transient response.
The output signals interface with ADP3415 MOSFET drivers,
which that are optimized for high speed and high efficiency. The
ADP3205 is capable of providing synchronous rectification control
to extend battery lifetime in light load conditions.
The ADP3205 is specified over the extended commercial temperature
range of 0°C to 100°C and is available in a 40-lead LFCSP package.
FUNCTIONAL BLOCK DIAGRAM
REV. 0
DRV3 DRVLSD3
39 38
DRV2 DRVLSD2
37 36
DRV1 DRVLSD1
35 34
ADP3205
TSYNC 40
PSI
HYSSET
HYS/CLIM
CONTROL
AND
CS MUX/
PHASE CONTROL
CLIM/ZCS
CMP
CORE
CMP
VDACREF CURRENT
HYSTERESIS SET
AND
SENSE
MUX
CLIM SET
VBG
DPSLP
VREF
BOOTSET
DPRSET
DPRSLP
VID5
VID4
VID3
VID2
VID1
VID0
PWRGD
CLKEN
TPWRGD
DPWRGD
SS 19
VREF
DRVCTRL
VBG
BOOT
REF
MUX
DAC
RES
NETWORK
VREF VBG
PRWGD
DELAY
BOOT
PRWGD
MASKING
MASK
PWRGD
COREGD
LATCH
EOFSS
SS/LATCH-OFF
TIMER
DRVCTRL
ALARM
LATCHEN
SD
VCC 22
GND
UVLO CMP
BIAS ENABLER
ALARM RST
BAND GAP
AND
REF AMP
VREF
VBG
RST
DPSHIFT
SET
CORE ABOVE CMP
CORE BELOW CMP
DVP CMP
OVP
LATCH
VOV
RVP
LATCH
RVP CMP
VRV
33 CS3
CS2
CS1
CS+
CS–
RAMP
REG
DPSHIFT
DACREF
DACREFFB
COREFB
CLAMP
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
1 page  
ABSOLUTE MAXIMUM RATINGS*
Input Supply Voltage (VCC) . . . . . . . . . . . . . . . . –0.3 V to +7 V
All Other Inputs/Outputs . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Operating Ambient Temperature Range . . . . . . . 0°C to 100°C
Junction Temperature Range . . . . . . . . . . . . . . . . 0°C to 150°C
Junction-to-Ambient Thermal Resistance . . . . . . . . . . 98°C/W
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability. Absolute maximum ratings
apply individually only, not in combination. Unless otherwise specified all other
voltages are referenced to GND.
Model
ADP3205JCP-Reel
ORDERING GUIDE
Temperature Package Package Quantity
Range
Description Option per Reel
0°C to 100°C LFCSP-40 CP-40 2500
ADP3205
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADP3205 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. 0
–5–
5 Page 
ADP3205
THEORY OF OPERATION
Theoretical Background
Featuring a new proprietary single or multiple phase buck converter
hysteretic control architecture developed by Analog Devices, Inc.,
the ADP3205 is the optimal core voltage control solution for
IMVP-IV Intel® mobile microprocessors.
The theoretical background for single and multiple phase dc-to-dc
converters using the ADP3205 for Intel mobile CPUs is presented
below. The ADP3205 features multiphase ripple regulators (also
called hysteretic regulators), which allow employing the ADOPT
(Analog Devices’ Optimal Voltage Positioning) technique to
implement the desired output voltage and load line, both statically
and dynamically, as required by Intel’s IMVPs specifications.
VIN
Q1
VSW
Q2
VH
VOUT
VH
L IL
CO
RE
+
VOUT
LOAD
VSW
VREF
IL
t
t
The implementation requires adding a resistive divider (RC and RD)
between the reference voltage and the output, and connecting
the tap of the divider to the noninverting input of the hysteretic
comparator. A capacitor, COC, is placed across the upper member
(RC) of the divider.
It is easily shown that the output impedance of the converter can
be no less than the ESR of the output capacitor. A straightforward
derivation demonstrates that the output impedance of the conver-
ter can be minimized to equal the ESR, RE, when the following
two equations are valid (neglecting PCB trace resistance for now):
RD = RE – RCS
RC RCS
and
COC
=
CO RE 2
RCS RD
(1)
(2)
From (2), the series resistance is:
RCS
=
RE
1 + RD
RC
(3)
This is the ADOPT configuration and design procedure that
allows the maximum possible ESR to be used while meeting a
given load-line specification.
t
Figure 1. Conventional Hysteretic Regulator
and Its Characteristic Waveforms
Figure 1 shows the conventional single-phase hysteretic regulator
and the characteristic waveforms. The operation is as follows.
During the time the upper transistor, Q1, is turned on, the inductor
current, IL, and also the output voltage, VOUT, increase. When
VOUT reaches the upper threshold of the hysteretic comparator,
Q1 is turned off, Q2 is turned on, and the inductor current and
output voltage begin to decrease. The cycle repeats after VOUT
reaches the lower threshold of the hysteretic comparator.
Since there is no voltage-error amplifier in the hysteretic regulator,
its response to any change in the load current or the input voltage
is virtually instantaneous. Therefore, the hysteretic regulator repre-
sents the fastest possible dc-to-dc converter control technique.
A disadvantage of the conventional hysteretic regulator is that its
frequency varies proportionally with the ESR, RE, of the output
capacitor. Since the initial value is often poorly controlled, and
the ESR of electrolytic capacitors also changes with temperature
and age, practical ESR variations can easily lead to a frequency
variation in the order of one to three. However, a modification of
the hysteretic topology eliminates the dependence of the operating
frequency on the ESR. In addition, the modification allows the
optimal implementation, ADOPT, of Intel’s IMVP-IV load-line
specifications.
VIN
Q1
Q2
VH
L IL
RCS
COC
RC
VOUT
CO
+
LOAD
RE
RD
+
–VREF
Figure 2. Modified Hysteretic Regulator with ADOPT
It can be seen from Equation 3 that unless RD is zero or RC is
infinite, RCS will be always smaller than RE. An advantage of the
circuit of Figure 2 is that if we select the ratio RD/RC well above
unity, the additional dissipation introduced by the series resistance
RCS will be negligible. Another interesting feature of the circuit
in Figure 2 is that the ac voltage across the two inputs of the
hysteretic comparator is now equal only to the ac voltage across
RCS. This is due to the presence of the capacitor COC, which
effectively couples the ac component of the output voltage to the
noninverting input voltage of the comparator. Since the compara-
tor sees only the ac voltage across RCS, in the circuit of Figure 2,
the dependence of the switching frequency on the ESR of the
output capacitor is completely eliminated. Equation 4 presents
the expression for the switching frequency.
( )f = RCS VIN −VOUT VOUT
LVH
VIN
(4)
Multiphase converters have certain, very important advantages,
including reduced rms current in the input filter capacitor
(allowing the use of a smaller and less expensive device), distrib-
uted heat dissipation (reducing the hot-spot temperature and
increasing reliability), higher total power capability, increased
equivalent frequency without increased switching losses (allowing
the use of smaller equivalent inductances and thereby shortening
the load transient time), and reduced ripple current in the output
capacitor (reducing the output ripple voltage and allowing the use
of smaller and less expensive output capacitors). Also, they have
some disadvantages that should be considered when choosing the
number of phases. Those disadvantages include the need for more
switches and output inductors than in a single-phase design (lead-
ing to higher cost than a single-phase solution, at least below a
certain power level), more complex control, and the possibility of
uneven current sharing among the phases.
The ADP3205 controller alleviates two of the above disadvantages
of multiphase converters. It presents a simple and cost-effective
control solution and provides perfect current sharing among the
phases. A simplified block diagram of a three-phase converter
REV. 0
–11–
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet ADP3205.PDF ] | |
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