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ADP3367 데이터시트 PDF




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부품번호 ADP3367 기능
기능 +5 V Fixed/ Adjustable Low-Dropout Linear Voltage Regulator
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ADP3367 데이터시트, 핀배열, 회로
a
+5 V Fixed, Adjustable
Low-Dropout Linear Voltage Regulator
ADP3367*
FEATURES
Low Dropout: 150 mV @ 200 mA
Low Dropout: 300 mV @ 300 mA
Low Power CMOS: 17 A Quiescent Current
Shutdown Mode: 0.2 A Quiescent Current
300 mA Output Current Guaranteed
Pin Compatible with MAX667
Stable with 10 F Load Capacitor
+2.5 V to +16.5 V Operating Range
Low Battery Detector
Fixed +5 V or Adjustable Output
High Accuracy: ؎2%
Dropout Detector Output
Low Thermal Resistance Package*
ESD > 6000 V
APPLICATIONS
Handheld Instruments
Cellular Telephones
Battery Operated Devices
Portable Equipment
Solar Powered Instruments
High Efficiency Linear Power Supplies
GENERAL DESCRIPTION
The ADP3367 is a low-dropout precision voltage regulator that
can supply up to 300 mA output current. It can be used to give
a fixed +5 V output with no additional external components or
can be adjusted from +1.3 V to +16 V using two external
resistors. Fixed or adjustable operation can be selected via the
SET input. The low quiescent current (17 µA) in conjunction
with the standby or shutdown mode (0.2 µA) makes this device
especially suitable for battery powered systems. The dropout
voltage when supplying 100 µA is only 15 mV allowing opera-
tion with minimal headroom thereby prolonging the useful bat-
tery life. At higher output current levels the dropout remains
low increasing to just 150 mV when supplying 200 mA. A wide
input voltage range from 2.5 V to 16.5 V is allowable. Addi-
tional features include a dropout detector and a low supply/bat-
tery monitoring comparator. The dropout detector can be used
to signal loss of regulation while the low battery detector can be
used to monitor the input supply voltage.
The ADP3367 is a much improved pin-compatible replacement
for the MAX667. Improvements include lower supply current,
tighter voltage accuracy and superior line and load regulation.
Improved ESD protection (>6000 V) is achieved by advanced
voltage clamping structures. The ADP3367 is specified over the
industrial temperature range –40°C to +85°C and is available in
narrow surface mount (SOIC) packages.
*Patent pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
IN
SHDN
LBO
LBI
GND
ADP3367
OUT
DD
A1
C2
1.255V
REF
SET
C1
50mV
TYPICAL OPERATING CIRCUIT
+6V
INPUT +
IN OUT
ADP3367
SET GND SHDN
+ C1
10µF
+5V
OUTPUT
400
TA = +50°C
300 GUARANTEED 300mA
200
ADP3367
DISSIPATION LIMIT
100
0
0
STANDARD
SO PACKAGE
DISSIPATION LIMIT
5 10
VIN–VOUT – V
15
Load Current vs. Input-Output Differential Voltage
ADI’s proprietary Thermal Coastline leadframe used in ADP3367AR
packaging, has 30% lower thermal resistance than the standard
leadframes. This improvement in heat flow rate results in lower
die temperature hence improves reliability.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703




ADP3367 pdf, 반도체, 판매, 대치품
ADP3367–Typical Performance Characteristics
500
TA = +25°C
2.5
TA = +25°C
VIN = 6V
2.0 CL = 10µF
1.5
250
1.0
10
1
100 200
LOAD CURRENT – mA
300
Figure 2. Dropout Voltage vs. Load Current
0.5
0.0
0
50 100 150
1 – mA
200
Figure 5. Load Regulation (DVOUT vs. DIOUT)
10
VIN = 6V
TA = +25°C
1
TA = +25°C
VIN
+10V
+6V
0.1
0.01
0.01
0.1
1 10
IOUT – mA
100 1000
Figure 3. Ground Current vs. Load Current
1000
100
20mA
10mA
10
5mA
2mA
TA = +25°C
100mA
50mA
1
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45
I-O DIFFERENCE – mV
Figure 4. DD Output Current vs. I-O Differential
VOUT
CH1 2.00V CH2 200mV M 2.00ms
200mV
0V
Figure 6. Dynamic Response to Input Change
OUTPUT
CURRENT
VOUT
100mA
10mA
20mV
0V
CH1 1.00V CH2 20.0mV M 2.00ms
Figure 7. Dynamic Response to Load Change
–4– REV. 0

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ADP3367 전자부품, 판매, 대치품
ADP3367
This may be expressed in terms of power dissipation as follows:
PD = (TJ TA)/(θJA)
where:
TJ = Die Junction Temperature (°C)
TA = Ambient Temperature (°C)
PD = Power Dissipation (W)
θJA = Junction to Ambient Thermal Resistance (°C/W)
If the device is being operated at the maximum permitted ambi-
ent temperature of 85°C, the maximum power dissipation per-
mitted is:
PD (max) = (TJ (max) – TA)/(θJA)
PD (max) = (125 – 85)/(θJA)
= 40/θJA
where:
θJA = 98°C/W for the 8-pin SOIC (R-8) package
Therefore, for a maximum ambient temperature of 85°C
PD (max) = 408 mW for R-8
At lower ambient temperatures the maximum permitted power
dissipation increases accordingly up to the maximum limits
specified in the absolute maximum specifications.
The thermal impedance (θJA) figures given are measured in still
air conditions and are reduced considerably where fan assisted
cooling is employed. Other techniques for reducing the thermal
impedance include large contact pads on the printed circuit
board and wide traces. The copper will act as a heat exchanger
thereby reducing the effective thermal impedance.
POWER DISSIPATION
Low Thermal Resistance Package
The ADP3367 utilizes a patented and proprietary Thermal
Coastline Leadframe which offers significantly lower resistance
to heat flow from die to the PC board.
Heat generated on the die is removed and transferred to the PC
board faster resulting in lower die temperature than standard
packages. Table II is a performance comparison between and
standard and Thermal Coastline package.
Table I. Thermal Resistance Performance Comparison*
Standard Package (SO-8) Thermal Coastline Package
θJC 44°C/W
θJA 170°C/W
PD 235 mW
40°C/W
98°C/W
408 mW
*Data presented in Table II is obtained using SEMI Standard Method G38-47
and SEMI Standard Specification G42-88.
A device operating at room temperature, +25°C, and +125°C
junction temperature can dissipate 1.15 W.
To maintain this high level of heat removal efficiency, once heat
is removed from the die to the PC board, it should be dissipated
to the air or other mediums to maintain the largest possible tem-
perature differential between the die and PC board; remember,
the rate at which heat is transferred is directly proportional to
the temperature differential.
Various PC board layout techniques could be used to remove
the heat from the immediate vicinity of the package. Consider
the following issues when designing a board layout:
1. PC board traces with larger copper cross section areas will
remove more heat; use PCs with thicker copper and/or wider
traces.
2. Increase the surface area exposed to open air so heat can be
removed by convection or forced air flow.
3. Use larger masses such as heat sinks or thermally conductive
enclosures to distribute and dissipate the heat.
4. Do not solder mask or silk screen the heat dissipating traces;
black anodizing will significantly improve heat dissipation by
means of increased radiation.
High Power Dissipation Recommendations
Where excessive power dissipation due to high input-output
differential voltages and/or high current conditions exists, the
simplest method of reducing the power requirements on the
regulator is to use a series dropper resistor. In this way the
excess power can be dissipated in the external resistor. As an
example, consider an input voltage of +12 V and an output
voltage requirement of +5 V @ 100 mA with an ambient tem-
perature of +85°C. The package power dissipation under these
conditions is 700 mW which exceeds the maximum ratings. By
using a dropper resistor to drop 4 V, the power dissipation
requirement for the regulator is reduced to 300 mW which is
within the maximum specifications for the SO-8 package at
85°C. The resistor value is calculated as R = 4/0.1 = 40 . A
resistor power rating of 1/2 W or greater may be used.
40
VIN 0.5W
IN
OUT
12V C1 +
1µF ADP3367
+ C2
10µF
+5V
OUTPUT
SET GND SHDN
Figure 14. Reducing Regulator Power Dissipation
Transient Response
The ADP3367 exhibits excellent transient performance as illus-
trated in the “Typical Performance Characteristics.” Figure 6
shows that an input step from 10 V to 6 V results in a very small
output disturbance (50 mV). Adding an input capacitor would
improve this even more.
Figure 7 shows how quickly the regulator recovers from an out-
put load change from 10 mA to 100 mA. The offset due to the
load current change is less than 1 mV.
Monitored µP Power Supply
Figure 15 shows the ADP3367 being used in a monitored µP
supply application. The ADP3367 supplies +5 V for the micro-
REV. 0
–7–

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ADP3367

+5 V Fixed/ Adjustable Low-Dropout Linear Voltage Regulator

Analog Devices
Analog Devices

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