AD808 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 AD808
기능 Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming
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AD808 데이터시트, 핀배열, 회로
a Fiber Optic Receiver with Quantizer and
Clock Recovery and Data Retiming
Meets CCITT G.958 Requirements
for STM-4 Regenerator—Type A
Meets Bellcore TR-NWT-000253 Requirements for OC-12
Output Jitter: 2.5 Degrees RMS
622 Mbps Clock Recovery and Data Retiming
Accepts NRZ Data, No Preamble Required
Phase-Locked Loop Type Clock Recovery—
No Crystal Required
Quantizer Sensitivity: 4 mV
Level Detect Range: 10 mV to 40 mV, Programmable
Single Supply Operation: +5 V or –5.2 V
Low Power: 400 mW
10 KH ECL/PECL Compatible Output
Package: 16-Lead Narrow 150 mil SOIC
The AD808 provides the receiver functions of data quantiza-
tion, signal level detect, clock recovery and data retiming for
622 Mbps NRZ data. The device, together with a PIN
diode/preamplifier combination, can be used for a highly inte-
grated, low cost, low power SONET OC-12 or SDH STM-4
fiber optic receiver.
The receiver front end signal level detect circuit indicates when
the input signal level has fallen below a user adjustable thresh-
old. The threshold is set with a single external resistor. The
signal level detect circuit 3 dB optical hysteresis prevents chatter
at the signal level detect output.
The PLL has a factory trimmed VCO center frequency and a
frequency acquisition control loop that combine to guarantee
frequency acquisition without false lock. This eliminates a reli-
ance on external components such as a crystal or a SAW filter,
to aid frequency acquisition.
The AD808 acquires frequency and phase lock on input data
using two control loops that work without requiring external
control. The frequency acquisition control loop initially acquires
the frequency of the input data, acquiring frequency lock on
random or scrambled data without the need for a preamble. At
frequency lock, the frequency error is zero and the frequency
detector has no further effect. The phase acquisition control
loop then works to ensure that the output phase tracks the input
phase. A patented phase detector has virtually eliminated pat-
tern jitter throughout the AD808.
The device VCO uses a ring oscillator architecture and patented
low noise design techniques. Jitter is 2.5 degrees rms. This low
jitter results from using a fully differential signal architecture,
Power Supply Rejection Ratio circuitry and a dielectrically
isolated process that provides immunity from extraneous signals
on the IC. The device can withstand hundreds of millivolts of
power supply noise without an effect on jitter performance.
The user sets the jitter peaking and acquisition time of the PLL
by choosing a damping factor capacitor whose value determines
loop damping. CCITT G.958 Type A jitter transfer require-
ments can easily be met with a damping factor of 5 or greater.
Device design guarantees that the clock output frequency will
drift by less than 20% in the absence of input data transitions.
Shorting the damping factor capacitor, CD, brings the clock
output frequency to the VCO center frequency.
The AD808 consumes 400 mW and operates from a single
power supply at either +5 V or –5.2 V.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site:
Fax: 781/326-8703
© Analog Devices, Inc., 1998

AD808 pdf, 반도체, 판매, 대치품
Maximum, Minimum and Typical Specifications
Specifications for every parameter are derived from statistical
analyses of data taken on multiple devices from multiple wafer
lots. Typical specifications are the mean of the distribution of
the data for that parameter. If a parameter has a maximum (or a
minimum), that value is calculated by adding to (or subtracting
from) the mean six times the standard deviation of the distribu-
tion. This procedure is intended to tolerate production varia-
tions: if the mean shifts by 1.5 standard deviations, the remaining
4.5 standard deviations still provide a failure rate of only 3.4 parts
per million. For all tested parameters, the test limits are guard-
banded to account for tester variation to thus guarantee that no
device is shipped outside of data sheet specifications.
Input Sensitivity and Input Overdrive
Sensitivity and Overdrive specifications for the Quantizer in-
volve offset voltage, gain and noise. The relationship between
the logic output of the quantizer and the analog voltage input is
shown in Figure 1.
For sufficiently large positive input voltage the output is always
Logic 1 and similarly, for negative inputs, the output is always
Logic 0. However, the transitions between output Logic Levels
1 and 0 are not at precisely defined input voltage levels, but
occur over a range of input voltages. Within this Zone of Confu-
sion, the output may be either 1 or 0, or it may even fail to attain
a valid logic state. The width of this zone is determined by the
input voltage noise of the quantizer (1.5 mV at the 1 × 10–10
confidence level). The center of the Zone of Confusion is the
quantizer input offset voltage (1 mV typ). Input Overdrive is the
magnitude of signal required to guarantee correct logic level
with 1 × 10–10 confidence level.
With a single-ended PIN-TIA (Figure 3), ac coupling is used
and the inputs to the Quantizer are dc biased at some common-
mode potential. Observing the Quantizer input with an oscillo-
scope probe at the point indicated shows a binary signal with
average value equal to the common-mode potential and instan-
taneous values both above and below the average value. It is
convenient to measure the peak-to-peak amplitude of this signal
and call the minimum required value the Quantizer Sensitivity.
Referring to Figure 1, since both positive and negative offsets
need to be accommodated, the Sensitivity is twice the Over-
drive. The AD808 Quantizer has 4 mV Sensitivity typical.
With a differential TIA (Figure 3), Sensitivity seems to improve
from observing the Quantizer input with an oscilloscope probe.
This is an illusion caused by the use of a single-ended probe. A
2 mV peak-to-peak signal appears to drive the AD808 Quan-
tizer. However, the single-ended probe measures only half the
signal. The true Quantizer input signal is twice this value since
the other Quantizer input is a complementary signal to the sig-
nal being observed.
Response Time
Response time is the delay between removal of the input signal
and indication of Loss of Signal (LOS) at SDOUT. The re-
sponse time of the AD808 (1.5 µs maximum) is much faster
than the SONET/SDH requirement (3 µs response time
100 µs). In practice, the time constant of the ac coupling at the
Quantizer input determines the LOS response time.
Nominal Center Frequency
This is the frequency at which the VCO will oscillate with the
loop damping capacitor, CD, shorted.
Tracking Range
This is the range of input data rates over which the AD808 will
remain in lock.
Capture Range
This is the range of input data rates over which the AD808 will
acquire lock.
Static Phase Error
This is the steady-state phase difference, in degrees, between the
recovered clock sampling edge and the optimum sampling in-
stant, which is assumed to be halfway between the rising and
falling edges of a data bit. Gate delays between the signals that
define static phase error, and IC input and output signals pro-
hibit direct measurement of static phase error.
Data Transition Density, ρ
This is a measure of the number of data transitions, from “0” to
“1” and from “1” to “0,” over many clock periods. ρ is the ratio
(0 ≤ ρ ≤ 1) of data transitions to bit periods.
This is the dynamic displacement of digital signal edges from
their long term average positions, measured in degrees rms or
Unit Intervals (UI). Jitter on the input data can cause dynamic
phase errors on the recovered clock sampling edge. Jitter on the
recovered clock causes jitter on the retimed data.
Output Jitter
This is the jitter on the retimed data, in degrees rms, due to a
specific pattern or some pseudorandom input data sequence
(PRN Sequence).
Jitter Tolerance
Jitter Tolerance is a measure of the AD808’s ability to track a
jittery input data signal. Jitter on the input data is best thought
of as phase modulation, and is usually specified in unit intervals.
The PLL must provide a clock signal that tracks the phase
modulation in order to accurately retime jittered data. In order
for the VCO output to have a phase modulation that tracks the
input jitter, some modulation signal must be generated at the
output of the phase detector. The modulation output from the
phase detector can only be produced by a phase error between
its data input and its clock input. Hence, the PLL can never
perfectly track jittered data. However, the magnitude of the
phase error depends on the gain around the loop. At low fre-
quencies, the integrator of the AD808 PLL provides very high
gain, and thus very large jitter can be tracked with small phase
errors between input data and recovered clock. At frequencies
closer to the loop bandwidth, the gain of the integrator is much
smaller, and thus less input jitter can be tolerated. The AD808
output will have a bit error rate less than 1 × 10–10 when in lock
and retiming input data that has the CCITT G.958 specified
jitter applied to it.
Jitter Transfer (Refer to Figure 14)
The AD808 exhibits a low-pass filter response to jitter applied
to its input data.
This describes the frequency at which the AD808 attenuates
sinusoidal input jitter by 3 dB.
This describes the maximum jitter gain of the AD808 in dB.
–4– REV. 0


AD808 전자부품, 판매, 대치품
The quantizer (comparator) has three gain stages, providing a
net gain of 350. The quantizer takes full advantage of the Extra
Fast Complementary Bipolar (XFCB) process. The input stage
uses a folded cascode architecture to virtually eliminate pulse
width distortion, and to handle input signals with common-
mode voltage as high as the positive supply. The input offset
voltage is factory trimmed and is typically less than 1 mV. XFCB’s
dielectric isolation allows the different blocks within this mixed-
signal IC to be isolated from each other, hence the 4 mV Sensi-
tivity is achieved. Traditionally, high speed comparators are
plagued by crosstalk between outputs and inputs, often resulting
in oscillations when the input signal approaches 10 mV. The
AD808 quantizer toggles at 2 mV (4.0 mV sensitivity) at the
input without making bit errors. When the input signal is low-
ered below 2 mV, circuit performance is dominated by input
noise, and not crosstalk.
Signal Detect
The input to the signal detect circuit is taken from the first stage
of the quantizer. The input signal is first processed through a
gain stage. The output from the gain stage is fed to both a posi-
tive and a negative peak detector. The threshold value is sub-
tracted from the positive peak signal and added to the negative
peak signal. The positive and negative peak signals are then
compared. If the positive peak, POS, is more positive than the
negative peak, NEG, the signal amplitude is greater than the
threshold, and the output, SDOUT, will indicate the presence
of signal by remaining low. When POS becomes more negative
than NEG, the signal amplitude has fallen below the threshold,
and SDOUT will indicate a loss of signal (LOS) by going high.
The circuit provides hysteresis by adjusting the threshold level
higher by a factor of two when the low signal level is detected.
This means that the input data amplitude needs to reach twice
the set LOS threshold before SDOUT will signal that the data is
again valid. This corresponds to a 3 dB optical hysteresis.
Figure 11. Signal Level Detect Circuit Block Diagram
Phase-Locked Loop
The phase-locked loop recovers clock and retimes data from
NRZ data. The architecture uses a frequency detector to aid
initial frequency acquisition; refer to Figure 12 for a block dia-
gram. Note the frequency detector is always in the circuit. When
the PLL is locked, the frequency error is zero and the frequency
detector has no further effect. Since the frequency detector is
always in the circuit, no control functions are needed to initiate
acquisition or change mode after acquisition.
Figure 12. PLL Block Diagram
The frequency detector delivers pulses of current to the charge
pump to either raise or lower the frequency of the VCO. During
the frequency acquisition process the frequency detector output
is a series of pulses of width equal to the period of the VCO.
These pulses occur on the cycle slips between the data fre-
quency and the VCO frequency. With a maximum density data
pattern (1010 . . . ), every cycle slip will produce a pulse at the
frequency detector output. However, with random data, not
every cycle slip produces a pulse. The density of pulses at the
frequency detector output increases with the density of data
transitions. The probability that a cycle slip will produce a pulse
increases as the frequency error approaches zero. After the fre-
quency error has been reduced to zero, the frequency detector
output will have no further pulses. At this point the PLL begins
the process of phase acquisition, with a settling time of roughly
2000 bit periods.
Jitter caused by variations of density of data transitions (pattern
jitter) is virtually eliminated by use of a new phase detector
(patented). Briefly, the measurement of zero phase error does
not cause the VCO phase to increase to above the average run
rate set by the data frequency. The jitter created by a 27–1 pseu-
dorandom code is 1/2 degree, and this is small compared to
random jitter.
The jitter bandwidth for the PLL is 0.06% of the center fre-
quency. This figure is chosen so that sinusoidal input jitter at
350 Hz will be attenuated by 3 dB.
The damping ratio of the PLL is user programmable with a
single external capacitor. At 622 MHz, a damping ratio of 5 is
obtained with a 0.47 µF capacitor. More generally, the damping
ratio scales as (fDATA × CD)1/2.
A lower damping ratio allows a faster frequency acquisition;
generally the acquisition time scales directly with the capacitor
value. However, at damping ratios approaching one, the acquisi-
tion time no longer scales directly with capacitor value. The
acquisition time has two components: frequency acquisition and
phase acquisition. The frequency acquisition always scales with
capacitance, but the phase acquisition is set by the loop band-
width of the PLL and is independent of the damping ratio. In
practice the acquisition time is dominated by the frequency
acquisition. The fractional loop bandwidth of 0.06% should
give an acquisition time of 2000 bit periods. However, the
actual acquisition time is several million bit periods and is
comprised mostly of the time needed to slew the voltage on
the damping capacitor to final value.
REV. 0


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