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AD8116 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD8116은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 AD8116 자료 제공

부품번호 AD8116 기능
기능 200 MHz / 16 x 16 Buffered Video Crosspoint Switch
제조업체 Analog Devices
로고 Analog Devices 로고


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AD8116 데이터시트, 핀배열, 회로
a
200 MHz, 16 ؋ 16 Buffered
Video Crosspoint Switch
AD8116
FEATURES
Large 16 ؋ 16 High Speed Nonblocking Switch Array
Switch Array Controllable via an 80-Bit Serial Word
Serial Data Out Allows “Daisy Chaining” of Multiple
AD8116s to Create Large Switch Arrays Over 256 ؋ 256
Complete Solution
Buffered Inputs
16 Individual Output Amplifiers
Drives 150 Loads
Excellent Video Performance
60 MHz 0.1 dB Gain Flatness
0.01% Differential Gain Error (RL = 150 )
0.01؇ Differential Phase Error (RL = 150 )
Excellent AC Performance
200 MHz –3 dB Bandwidth
300 V/s Slew Rate
Low Power of 900 mW (3.5 mW per Point)
Low All Hostile Crosstalk of –70 dB @ 5 MHz
Output Disable Allows Direct Connection of Multiple
Device Outputs
Chip Enable Allows Selection of Individual AD8116s in
Large Arrays (or Parallel Programming of AD8116s)
Reset Pin Allows Disabling of All Outputs (Connected
Through a Capacitor to Ground Provides “Power-
On” Reset Capability)
128-Lead LQFP Package (14 mm ؋ 14 mm)
APPLICATIONS
Routing of High Speed Signals Including:
Composite Video (NTSC, PAL, S, SECAM, etc.)
Component Video (YUV, RGB, etc.)
3-Level Digital (HDB3)
Video on Demand
Ultrasound
Communication Satellites
PRODUCT DESCRIPTION
The AD8116 is a high speed 16 × 16 video crosspoint switch
matrix. It offers a –3 dB signal bandwidth greater than 200 MHz
and channel switch times of 60 ns with 0.1% settling. With –70dB
of crosstalk and –1 dB of isolation (@ 5 MHz), the AD8116
is useful in many high speed applications. The differential gain
and differential phase errors of better than 0.01% and 0.01°,
respectively, along with 0.1 dB flatness out to 60 MHz make the
AD8116 ideal for video signal switching.
The AD8116 includes output buffers that can be placed into a
high impedance state for paralleling crosspoint outputs so that
off channels do not load the output bus. It operates on voltage
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
AD8116
CLK
CLK
DATA IN
UPDATE
CE
RESET
16 INPUTS
80-BIT SHIFT REG.
80
PARALLEL LATCH
80
DECODE
16 ؋ 5:16 DECODERS
16
256
SWITCH
MATRIX
OUTPUT
BUFFER
+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
DATA OUT
UPDATE
CE
RESET
16 OUTPUTS
4
RL = 50
3
0.5
0.4
2 0.3
1 0.2
200mV p-p
0 0.1
–1
FLATNESS
2V p-p
0
–2
–3
–4
100k
2V p-p
200mV p-p
1M
10M
100M
FREQUENCY – Hz
Figure 1. Frequency Response
–0.1
–0.2
–0.3
1G
supplies of ± 5 V while consuming only 90 mA of idle current.
The channel switching is performed via a serial digital control
that can accommodate “daisy chaining” of several devices.
The AD8116 is packaged in a 128-lead LQFP package occupy-
ing only 0.36 square inches, and is specified over the commer-
cial temperature range of 0°C to 70°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




AD8116 pdf, 반도체, 판매, 대치품
AD8116
TIMING CHARACTERISTICS
Parameter
Data Setup Time
CLK Pulsewidth
Data Hold Time
CLK Pulse Separation
CLK to UPDATE Delay
UPDATE Pulsewidth
CLK to DATA OUT Valid
Propagation Delay, UPDATE to Switch On or Off
Data Load Time, CLK = 5 MHz
CLK, UPDATE Rise and Fall Times
RESET Time
Symbol
t1
t2
t3
t4
t5
t6
t7
Min
20
100
20
100
0
50
Limit
Typ
16
Max
200
50
100
200
Unit
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
1
CLK
0
1
DATA IN
0
1 = LATCHED
UPDATE
0 = TRANSPARENT
DATA OUT
t2
t1 t3
OUT15 (D4)
t7
t4
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
OUT15 (D3)
OUT00 (D0)
t5
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
t6
CLOCK
DATA IN
0 1 2 3 4 5 6 7 8 9 10
15
20
25
75 79
UPDATE
T=0
INCREASING TIME
Figure 2. Timing Diagram and Programming Example
VIH
CLK, DATA IN,
CE, UPDATE
2.0 V min
VIL
CLK, DATA IN,
CE, UPDATE
VOH
DATA OUT
0.8 V max
2.7 V min
Table I. Logic Levels
VOL
DATA OUT
0.5 V max
IIH IIL IOH
CLK, DATA IN, CLK, DATA IN, DATA OUT
CE, UPDATE CE, UPDATE
20 μA max
–400 μA min
–400 μA max
IOL
DATA OUT
3.0 mA min
REV. C
–3–

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AD8116 전자부품, 판매, 대치품
AD8116
PIN FUNCTION DESCRIPTIONS
Pin Name
INxx
DATA IN
CLK
DATA OUT
UPDATE
Pin Numbers
2, 4, 6, 8, 10, 12, 14, 16, 18,
20, 22, 24, 26, 28, 30, 32
37, 126
36, 125
35, 124
38, 123
RESET
CE
OUTyy
AGND
DVCC
DGND
DVEE
AVEE
AVCC
AGNDxx
AVCC00
AVCC15
AVCCxx/yy
AVEExx/yy
39, 122
40, 121
65, 67, 69, 71, 73, 75, 77, 79,
81, 83, 85, 87, 89, 91, 93, 95
1, 3, 5, 7, 9, 11, 13, 15, 17, 19,
21, 23, 25, 27, 29, 31, 33, 128
34, 127
41, 120
42, 119
43, 44, 45, 116, 117, 118
46, 47, 48, 113, 114, 115
56–63, 97–104
96
64
68, 72, 76, 80, 84, 88, 92
66, 70, 74, 78, 82, 86, 90, 94
Pin Description
Analog Inputs; xx = Channel No. 00 thru 15.
Serial Data Input, TTL Compatible.
Serial Clock, TTL Compatible. Falling edge triggered.
Serial Data Out, TTL Compatible.
Enable (Transparent) “Low.” Allows serial register to connect directly to switch
matrix. Data latched when “high.”
Disable Outputs, Enable “Low.”
Chip Enable, Enable “Low.” Must be “low” to clock in & latch data.
Analog Outputs yy = Channel Nos. 00 thru 15.
Analog Ground for inputs and switch matrix.
+5 V for Digital Circuitry.
Ground for Digital Circuitry.
–5 V for Digital Circuitry.
–5 V for Inputs and Switch Matrix.
+5 V for Inputs and Switch Matrix.
Ground for Output Amp, xx = Output Channel Nos. 00 thru 15. Must be connected.
+5 V for Output Channel 00. Must be connected.
+5 V for Output Channel 15. Must be connected.
+5 V for Output Amplifier that is shared by Channel Nos. xx and yy. Must be connected.
–5 V for Output Amplifier that is shared by Channel Nos. xx and yy. Must be connected.
VCC
ESD
INPUT
ESD
VEE
a. Analog Input
VCC
ESD
INPUT
ESD
VEE
d. Logic Input
VCC
ESD
ESD
OUTPUT
VEE
b. Analog Output
VCC
ESD
RESET
ESD
20k
c. Reset Input
VCC
2k
ESD
ESD
OUTPUT
VEE
e. Logic Output
Figure 5. I/O Pin Schematics
–6– REV. C

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