PDF AD8369 Data sheet ( Hoja de datos )

Número de pieza	AD8369
Descripción	45 dB Digitally Controlled VGA LF to 600 MHz
Fabricantes	Analog Devices
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No Preview Available ! FEATURES Digitally Controlled Variable Gain in 3 dB Steps –5 dB to +40 dB (RL = 1 k⍀) –10 dB to +35 dB (RL = 200 ⍀) Less than 0.2 dB Flatness over a +20 MHz Bandwidth up to 380 MHz 4-Bit Parallel or 3-Wire Serial Interface Differential 200 ⍀ Input and Output Impedance Single 3.0 V–5.5 V Supply Draws 37 mA at 5 V Power-Down <1 mA Maximum APPLICATIONS Cellular/PCS Base Stations IF Sampling Receivers Fixed Wireless Access Wireline Modems Instrumentation 45 dB Digitally Controlled VGA LF to 600 MHz AD8369 FUNCTIONAL BLOCK DIAGRAM BIT3 BIT2 BIT1 BIT0 DENB SENB 3dB STEP GAIN CODE DECODE BIAS Gm CELLS VPOS PWUP FILT OPHI OPLO INHI INLO COMM CMDC COMM PRODUCT DESCRIPTION The AD8369 is a high performance digitally controlled variable gain amplifier (VGA) for use from low frequencies to a –3 dB frequency of 600 MHz at all gain codes. The AD8369 delivers excellent distortion performance: the two-tone, third-order intermodulation distortion is –69 dBc at 70 MHz for a 1 V p-p composite output into a 1 kW load. The AD8369 has a nominal noise figure of 7 dB when at maximum gain, then increases with decreasing gain. Output IP3 is +19.5 dBm at 70 MHz into a 1 kW load and remains fairly constant over the gain range. The signal input is applied to pins INHI and INLO. Variable gain is achieved via two methods. The 6dB gain steps are implemented using a discrete X-AMP® structure, in which the input signal is palrsoogsreetsssitvheelyinapttuetniumapteeddabnycea; 2t0h0e 3WdRB-2stReplsadadreerimneptlwemoreknttehdata t the output of the amplifier. This combination provides very accurate 3dB gain steps over a span of 45 dB. The output imped- ance is set by on-chip resistors across the differential output pins, OPHI and OPLO. The overall gain depends upon the source and load impedances due to the resistive nature of the input and output ports. Digital control of the AD8369 is achieved using either a serial or a parallel interface. The mode of digital control is selected by connecting a single pin (SENB) to ground or the positive sup- ply. Digital control pins can be driven with standard CMOS logic levels. The AD8369 may be powered on or off by a logic level applied to the PWUP pin. For a logic high, the chip powers up rapidly to its nominal quiescent current of 37 mA at 25ºC. When low, the total dissipation drops to less than a few milliwatts. The AD8369 is fabricated on an Analog Devices proprietary, high performance 25 GHz silicon bipolar IC process and is available in a 16-lead TSSOP package for the industrial temperature range of –40rC to +85rC. A populated evaluation board is available. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page AD8369 SPECIFICATIONS (Continued) Parameter Frequency = 380 MHz Voltage Gain Gain Flatness Noise Figure Output IP3 IMD3 Harmonic Distortion P1dB Conditions Within ± 20 MHz of 380 MHz f1 = 379.55 MHz, f2 = 380.45 MHz f1 = 379.55 MHz, f2 = 380.45 MHz, VOPHI – VOPLO = 1 V p-p composite Second-Order, VOPHI – VOPLO = 1 V p-p Third-Order, VOPHI – VOPLO = 1 V p-p For ± 1 dB deviation from linear gain Specifications subject to change without notice. Min Typ 38.5 ± 0.15 7.8 +8.5 +8.5 –47 –45 –49 +0.5 +0.5 Max Unit dB dB dB dBV rms dBm dBc dBc dBc dBV rms dBm TIMING SPECIFICATIONS SERIAL PROGRAMMING TIMING REQUIREMENTS (VS = 5 V, T = 25rC) Parameter Typ Minimum Clock Pulsewidth (TPW) Minimum Clock Period (TCK) Minimum Setup Time Data vs. Clock (TDS) Minimum Setup Time Data Enable vs. Clock (TES) Minimum Hold Time Clock vs. Data Enable (TEH) Minimum Hold Time Data vs. Clock (TDH) 10 20 2 2 2 4 PARALLEL PROGRAMMING TIMING REQUIREMENTS (VS = 5 V, T = 25rC) Parameter Typ Minimum Setup Time Data Enable vs. Data (TES) Minimum Hold Time Data Enable vs. Data (TEH) Minimum Data Enable Width (TPW) 2 2 4 Unit ns ns ns ns ns ns Unit ns ns ns MSB (BIT3) DATA (BIT 0) CLOCK (BIT 1) TDS TDH MSB MSB–1 MSB–2 LSB TPW TCK DATA CLOCK ENABLE DISABLED (DENB) TES CLOCK ENABLED TEH CLOCK DISABLED DATA IS LATCHED ON LOW-TO-HIGH TRANSITION OF DENB (NOT TO SCALE) Serial Programming Timing MSB–1 (BIT2) MSB–2 (BIT1) LSB (BIT0) DENB TES TEH TPW DATA IS LATCHED ON HIGH-TO-LOW TRANSITION OF DENB (NOT TO SCALE) Parallel Programming Timing –4– REV. A 5 Page AD8369 90 120 60 150 180 210 750MHz GAIN CODE 15 10MHz 30 0 GAIN CODES 0, 1, AND 9 380MHz 500MHz 330 240 300 270 TPC 19. Differential Input Reflection Coefficient, S11, ZO = 50 W Differential, Selected Gain Codes DIFFERENTIAL OUTPUT 250mV/VERTICAL DIVISION AVERAGE OF 128 SAMPLES ZERO 90 120 60 150 180 210 750MHz GAIN CODE 15 10MHz 30 0 GAIN CODES 0, 1, AND 9 380MHz 500MHz 330 240 300 270 TPC 22. Differential Output Reflection Coefficient, S22, ZO = 50 W Differential, Selected Gain Codes INPUT = 250mV p-p, 10MHz OVERDRIVE ZERO OUTPUT 1V/VERTICAL DIVISION RECOVERY BIT 0 2V/VERTICAL DIVISION GND TIME – 20ns/DIV TPC 20. Gain Step Time Domain Response, 3 dB Step, VS = 5 V, RL = 1 kW, Parallel Transparent Mode ZERO DIFFERENTIAL OUTPUT 70MHz, 750mV/DIV GND BIT 3 2V/VERTICAL DIVISION TIME – 1␮s/DIV TPC 23. Overdrive Recovery, Maximum Gain, VS = 5 V, RL = 1 kW, Parallel Transparent Mode ZERO DIFFERENTIAL OUTPUT 200mV/DIV PWUP 2V/VERTICAL DIVISION GND TIME – 2␮s/DIV TPC 21. PWUP Time Domain Response, Maximum Gain, VS = 5 V, RL = 1 kW GND INPUT 2mV/DIV TIME – 20␮s/DIV TPC 24. Pulse Response, Maximum Gain, VS = 5 V, RL = 1 kW –10– REV. A 11 Page

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