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AD8600 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD8600은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 AD8600 자료 제공

부품번호 AD8600 기능
기능 16-Channel/ 8-Bit Multiplying DAC
제조업체 Analog Devices
로고 Analog Devices 로고


AD8600 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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AD8600 데이터시트, 핀배열, 회로
a
FEATURES
16 Independently Addressable Voltage Outputs
Full-Scale Set by External Reference
2 µs Settling Time
Double Buffered 8-Bit Parallel Input
High Speed Data Load Rate
Data Readback
Operates from Single +5 V
Optional ±6 V Supply Extends Output Range
APPLICATIONS
Phased Array Ultrasound & Sonar
Power Level Setting
Receiver Gain Setting
Automatic Test Equipment
LCD Clock Level Setting
16-Channel, 8-Bit
Multiplying DAC
AD8600*
FUNCTIONAL BLOCK DIAGRAM
CS
EN
A3
A2
A1
A0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
R/W RS VDD1 LD VDD2
CONTROL
LOGIC
VREF VCC
ADDRESS
DECODE
16 x 8
INPUT
REGISTERS
16 x 8
DAC
REGISTERS
AD8600
16
8-BIT
DACS
DGND1
DGND2 DACGND VEE
O0
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
O13
O14
O15
GENERAL DESCRIPTION
The AD8600 contains 16 independent voltage output digital-to-
analog converters that share a common external reference input
voltage. Each DAC has its own DAC register and input register
to allow double buffering. An 8-bit parallel data input, four ad-
dress pins, a CS select, a LD, EN, R/W, and RS provide the
digital interface.
The AD8600 is constructed in a monolithic CBCMOS process
which optimizes use of CMOS for logic and bipolar for speed
and precision. The digital-to-analog converter design uses volt-
age mode operation ideally suited to single supply operation.
The internal DAC voltage range is fixed at DACGND to VREF.
The voltage buffers provide an output voltage range that ap-
proaches ground and extends to 1.0 V below VCC. Changes in
reference voltage values and digital inputs will settle within
± 1 LSB in 2 µs.
Data is preloaded into the input registers one at a time after the
internal address decoder selects the input register. In the write
mode (R/W low) data is latched into the input register during
the positive edge of the EN pulse. Pulses as short as 40 ns can
be used to load the data. After changes have been submitted to
the input registers, the DAC registers are simultaneously up-
dated by a common load EN × LD strobe. The new analog out-
put voltages simultaneously appear on all 16 outputs.
*Patent pending.
At system power up or during fault recovery the reset (RS) pin
forces all DAC registers into the zero state which places zero
volts at all DAC outputs.
The AD8600 is offered in the PLCC-44 package. The device is
designed and tested for operation over the extended industrial
temperature range of –40°C to +85°C.
R/WCS•ADDR•EN VDD1
VDD2 LDEN VREF
VCC
DB7...DB0
INPUT
REGISTER
DAC
REGISTER
R-2R
DAC
OX
RS
DGND2 RS DACGND
VEE
DGND1
R/WCS•ADDRESS
Figure 1. Equivalent DAC Channel
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703




AD8600 pdf, 반도체, 판매, 대치품
AD8600
ELECTRICAL CHARACTERISTICS (@ VDD1 = VDD2 = VCC = +5 V ± 5%, VEE = –5 V, VREF = +3.500 V, –40°C TA +85°C,
unless otherwise noted)
Parameter
Symbol
INTERFACE TIMING1, 2
Clock (EN) Frequency
Clock (EN) High Pulse Width
Clock (EN) LowPulse Width
Data Setup Time
Data Hold Time
Address Setup Time
Address Hold Time
Valid Address to Data Valid
Load Enable Setup Time
Load Enable Hold Time
Read/Write to Clock (EN)
Read/Write to DataBus Hi-Z
Read/Write to DataBus Active
Clock (EN) to Read/Write
Clock (EN) to Chip Select
Chip Select to Clock (EN)
Chip Select to Data Valid
Chip Select to DataBus Hi-Z
Reset Pulse Width
fCLK
tCH
tCL
tDS
tDH
tAS
tAH
tAD
tLS
tLH
tRWC
tRWZ
tRWD
tTWH
tTCH
tCSC
tCSD
tCSZ
tRS
NOTES
1Guaranteed by design not subject to production test.
2All logic input signals have maximum rise and fall times of 2 ns.
Specifications subject to change without notice.
Condition
Data Loading
Min Typ Max
12.5
40
40
40
10
0
0
160
0
0
30
120
120
0
0
30
120
150
25
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R/W
DATA
ADDR
EN
CS
tRWZ
tDS
tAS
tDH
tAH
tRWC
tCSC
tCH
tCL
tTWH
HIGH-Z
tTCH
R/W
tRWD
HIGH -Z
DATA
ADDR
EN
CS
tCSD
tAD
tCSZ
Figure 2. Write Timing
Figure 3. Readback Timing
LD
tLS
EN
tLH
tRS
RS
OUT
tS1
tS1
Figure 4. Write to DAC Register & Voltage Output Settling
Timing (CS= High, Prevents Input Register Changes)
–4–
REV. 0

4페이지










AD8600 전자부품, 판매, 대치품
+1/2
0
–1/2
+1/2
0
–1/2
DACs 00–07 SUPERIMPOSED
VCC = +5V
VEE = –5V
VREF = +3.5V
TA = +25°C
DACs 08–015 SUPERIMPOSED
0 64 128 192 256
DIGITAL INPUT CODE – Decimal
Figure 5. Linearity Error vs.
Digital Code
Typical Performances Characteristics–AD8600
3.50
3.49
VCC = +5V
VEE = –5V
VREF = 3.5V
3.48
3.47
–50 –25
0 25 50 75 100 125
TEMPERATURE – °C
Figure 6. Full-Scale Voltage vs.
Temperature
8
VCC = +5V
VEE = –5V
4 VREF = 3.5V
0
–2
–4
–50 –25
0 25 50 75 100 125
TEMPERATURE – °C
Figure 7. Zero-Scale Voltage vs.
Temperature
15 VCC = +5V
VEE = –5V
10 RS = 0
5
0
–5
–10
–15
–4 –3 –2 –1 0 1 2 3
VOUT – Volts
Figure 8. Output Current vs.
Voltage
4
4
3
2 VCC = +5V
VEE = –5V
VREF = 3.5V
1
0
TIME – 250ns/DIV
Figure 9. Full-Scale Settling Time
100
VCC = +5V
80
VEE = –5V
VREF = 0V
TA = +25°C
60
40
20
0
10 100 1k 10k
FREQUENCY – Hz
Figure 10. Voltage Noise Density vs.
Frequency
VIN = 100mV p-p + 2.5VDC
CODE = FFH
TA = +25°C
GAIN
00
–5 –45
–10 –90
PHASE
–15
1k 10k 100k 1M 10M
FREQUENCY – Hz
Figure 11. Gain & Phase vs.
Frequency
0
VIN = 2V p-p + 1VDC
–20 RS = 0
TA = +25°C
–40
–60
–80
–100
100
1k 10k
FREQUENCY – Hz
100k
Figure 12. AC Feedthrough vs.
Frequency
60
VCC = 100mV p-p
TA = +25°C
50
CODE = 00H
VEE = –5V
40
30
20
10
100 1k 10k
FREQUENCY – Hz
100k
Figure 13. PSRR vs. Frequency
REV. 0
–7–

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