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PDF AD876 Data sheet ( Hoja de datos )
| Número de pieza | AD876 | |
| Descripción | 10-Bit 20 MSPS 160 mW CMOS A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
CMOS 10-Bit 20 MSPS Sampling A/D Converter
Pin-Compatible 8-Bit Option
Power Dissipation: 160 mW
+5 V Single Supply Operation
Differential Nonlinearity: 0.5 LSB
Guaranteed No Missing Codes
Power Down (Standby) Mode
Three-State Outputs
Digital I/Os Compatible with +5 V or +3.3 V Logic
Adjustable Reference Input
Small Size: 28-Lead SOIC, 28-Lead SSOP, or 48-Lead
Thin Quad Flatpack (TQFP)
10-Bit 20 MSPS 160 mW
CMOS A/D Converter
AD876
FUNCTIONAL BLOCK DIAGRAM
CLK
AVDD DVDD DRVDD
SHA
AIN
SHA
GAIN SHA
GAIN SHA
GAIN
A/D
REFTF
REFTS
REFBS
REFBF
A/D D/A
AD876
A/D D/A
A/D D/A
CORRECTION LOGIC
OUTPUT BUFFERS
CML
AVSS DVSS DRVSS
STBY
THREE-
STATE
(MSB)
D9
D0
(LSB)
PRODUCT DESCRIPTION
The AD876 is a CMOS, 160 mW, 10-bit, 20 MSPS analog-to-
digital converter (ADC). The AD876 has an on-chip input
sample-and-hold amplifier. By implementing a multistage pipe-
lined architecture with output error correction logic, the AD876
offers accurate performance and guarantees no missing codes
over the full operating temperature range. Force and sense con-
nections to the reference inputs minimize external voltage drops.
The AD876 can be placed into a standby mode of operation
reducing the power below 50 mW. The AD876’s digital I/O
interfaces to either +5 V or +3.3 V logic. Digital output pins
can be placed in a high impedance state; the format of the out-
put is straight binary coding.
The AD876’s speed, resolution and single-supply operation
ideally suit a variety of applications in video, multimedia, imag-
ing, high speed data acquisition and communications. The
AD876’s low power and single-supply operation satisfy require-
ments for high speed portable applications. Its speed and reso-
lution ideally suit charge coupled device (CCD) input systems
such as color scanners, digital copiers, electronic still cameras
and camcorders.
The AD876 comes in a space saving 28-lead SOIC and 48-lead
thin quad flatpack (TQFP) and is specified over the commercial
(0°C to +70°C) temperature range.
PRODUCT HIGHLIGHTS
Low Power
The AD876 at 160 mW consumes a fraction of the power of
presently available 8- or 10-bit, video speed converters. Power-
down mode and single-supply operation further enhance its
desirability in low power, battery operated applications such
as electronic still cameras, camcorders and communication
systems.
Very Small Package
The AD876 comes in a 28-lead SOIC, 28-lead SSOP, and 48-
lead surface mount, thin quad flat package. The TQFP package
is ideal for very tight, low headroom designs.
Digital I/O Functionality
The AD876 offers three-state output control.
Pin Compatible Upgrade Path
The AD876 offers the option of laying out designs for eight
bits and migrating to 10-bit resolution if prototype results
warrant.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
1 page  
AD876
ABSOLUTE MAXIMUM RATINGS*
Parameter
With Respect to Min Max Units
AVDD
DVDD, DRVDD
AVSS
AIN
REFTS, REFTF
REFBS, REFBF
Digital Inputs, CLK
Junction Temperature
Storage Temperature
Lead Temperature
(10 sec)
AVSS
DVSS, DRVSS
DVSS, DRVSS
AVSS
AVSS
DVSS, DRVSS
–0.5 +6.5 Volts
–0.5 +6.5 Volts
–0.5 +0.5 Volts
–0.5 +6.5 Volts
–0.5 +6.5 Volts
–0.5 +6.5 Volts
+150 °C
–65 +150 °C
+300 °C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.
DVDD
DRVDD
DVDD
ORDERING GUIDE
Model
Temperature Package
Range
Description
Package
Options
AD876JR
AD876JST-Reel
AD876JR-8
AD876AR
AD876ARS
AD876JRS
AD876JRS-8
0°C to +70°C 28-Lead SOIC
R-28
0°C to +70°C 48-Lead TQFP ST-48
(Tape and Reel 13")
0°C to +70°C 28-Lead SOIC
R-28
–40°C to +85°C 28-Lead SOIC
R-28
–40°C to +85°C 28-Lead SSOP RS-28
0°C to +70°C 28-Lead SSOP RS-28
0°C to +70°C 28-Lead SSOP RS-28
DRVDD
DVDD
DRVDD
DVSS
a) D0–D9
DVSS
DRVSS
AVDD
AVSS
d) AIN
DVSS
DRVSS
b) Three-State, Standby
AVDD
REFTF
AVSS
AVDD
REFTS
AVSS
AVDD
REFBS
AVSS
AVDD
REFBF
AVSS
Figure 2. Equivalent Circuits
DVSS
DRVSS
c) CLK
INTERNAL
REFERENCE
VOLTAGE
INTERNAL
REFERENCE
VOLTAGE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD876 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. B
–5–
WARNING!
ESD SENSITIVE DEVICE
5 Page 
AD876
Table I. Output Data Format
Approx.
AIN (V)
>4
4
3
2
<2
X
THREE- DATA
STATE D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 1111111111
0 1111111111
0 1000000000
0 0000000000
0 0000000000
1 ZZZZZZZZZZ
A low power mode feature is provided such that for STBY =
HIGH and the clock disabled, the static power of the AD876
will drop below 50 mW.
GROUNDING AND LAYOUT RULES
As is the case for any high performance device, proper ground-
ing and layout techniques are essential in achieving optimal
performance. The analog and digital grounds on the AD876
have been separated to optimize the management of return
currents in a system. It is recommended that a printed circuit
board (PCB) of at least 4 layers employing a ground plane and
power planes be used with the AD876. The use of ground and
power planes offers distinct advantages:
1. The minimization of the loop area encompassed by a signal
and its return path.
2. The minimization of the impedance associated with ground
and power paths.
3. The inherent distributed capacitor formed by the power
plane, PCB insulation, and ground plane.
These characteristics result in both a reduction of electro-
magnetic interference (EMI) and an overall improvement in
performance.
It is important to design a layout which prevents noise from
coupling onto the input signal. Digital signals should not be run
in parallel with the input signal traces and should be routed
away from the input circuitry. Separate analog and digital
grounds should be joined together directly under the AD876. A
solid ground plane under the AD876 is also acceptable if the
power and ground return currents are managed carefully. A
general rule of thumb for mixed signal layouts dictates that the
return currents from digital circuitry should not pass through
critical analog circuitry. For further layout suggestions, see the
AD876 Evaluation Board data sheet.
For DRVDD = 5 V, the AD876 output signal swing is compat-
ible with both high speed CMOS and TTL logic families. For
TTL, the AD876 on-chip, output drivers were designed to
support several of the high speed TTL families (F, AS, S). For
applications where the clock rate is below 20 MSPS, other TTL
families may be appropriate. For interfacing with lower voltage
CMOS logic, the AD876 sustains 20 MSPS operation with
DRVDD = 3.3 V. In all cases, check your logic family data
sheets for compatibility with the AD876 Digital Specification
table.
THREE-STATE OUTPUTS
The digital outputs of the AD876 can be placed in a high im-
pedance state by setting the THREE-STATE pin to HIGH.
This feature is provided to facilitate in-circuit testing or
evaluation. Note that this function is not intended for enabling/
disabling the ADC outputs from a bus at 20 MSPS. Also, to
avoid corruption of the sampled analog signal during conversion
(3.5 clock cycles), it is highly recommended that the AD876
outputs be enabled on the bus prior to the first sampling. For
the purpose of budgetary timing, the maximum access and float
delay times (tDD, tHL shown in Figure 15) for the AD876 are
150 ns.
THREE-STATE
D0–D9
t DD
ACTIVE
t HL
HIGH IMPEDANCE
Figure 22. High-Impedance Output Timing Diagram
DIGITAL OUTPUTS
Each of the on-chip buffers for the AD876 output bits (D0–D9)
is powered from the DRVDD supply pins, separate from AVDD or
DVDD. The output drivers are sized to handle a variety of logic
families while minimizing the amount of glitch energy gener-
ated. In all cases, a fan-out of one is recommended to keep the
capacitive load on the output data bits below the specified 20 pF
level.
REV. B
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD876.PDF ] | |
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