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AD8804 데이터시트 PDF




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부품번호 AD8804 기능
기능 12 Channel/ 8-Bit TrimDACs with Power Shutdown
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AD8804 데이터시트, 핀배열, 회로
a
12 Channel, 8-Bit TrimDACs
with Power Shutdown
AD8802/AD8804
FEATURES
Low Cost
Replaces 12 Potentiometers
Individually Programmable Outputs
3-Wire SPI Compatible Serial Input
Power Shutdown <55 Watts Including IDD & IREF
Midscale Preset, AD8802
Separate VREFL Range Setting, AD8804
+3 V to +5 V Single Supply Operation
APPLICATIONS
Automatic Adjustment
Trimmer Replacement
Video and Audio Equipment Gain and Offset Adjustment
Portable and Battery Operated Equipment
GENERAL DESCRIPTION
The 12-channel AD8802/AD8804 provides independent digitally-
controllable voltage outputs in a compact 20-lead package. This
potentiometer divider TrimDAC® allows replacement of the
mechanical trimmer function in new designs. The AD8802/
AD8804 is ideal for dc voltage adjustment applications.
Easily programmed by serial interfaced microcontroller ports,
the AD8802 with its midscale preset is ideal for potentiometer
replacement where adjustments start at a nominal value. Appli-
cations such as gain control of video amplifiers, voltage con-
trolled frequencies and bandwidths in video equipment,
geometric correction and automatic adjustment in CRT com-
puter graphic displays are a few of the many applications ideally
suited for these parts. The AD8804 provides independent con-
trol of both the top and bottom end of the potentiometer divider
allowing a separate zero-scale voltage setting determined by the
VREFL pin. This is helpful for maximizing the resolution of
devices with a limited allowable voltage control range.
Internally the AD8802/AD8804 contains 12 voltage-output
digital-to-analog converters, sharing a common reference-
voltage input.
TrimDAC is a registered trademark of Analog Devices, Inc.
FUNCTIONAL BLOCK DIAGRAM
CS
CLK
SDI
SHDN
AD8802/AD8804
D11
D10
D9
D8
D7
SER
REG
EN
ADDR
DEC
D D0
8
D7
DAC
REG
#1
D0
R
D7
DAC
REG
#12
D0
R
DAC
1
DAC
12
GND
RS VREFL
(AD8802 ONLY) (AD8804 ONLY)
VDD
VREFH
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
Each DAC has its own DAC latch that holds its output state.
These DAC latches are updated from an internal serial-to-
parallel shift register that is loaded from a standard 3-wire
serial input digital interface. The serial-data-input word is
decoded where the first 4 bits determine the address of the DAC
latches to be loaded with the last 8 bits of data. The AD8802/
AD8804 consumes only 10 µA from 5 V power supplies. In ad-
dition, in shutdown mode reference input current consumption
is also reduced to 10 µA while saving the DAC latch settings for
use after return to normal operation.
The AD8802/AD8804 is available in the 20-pin plastic DIP, the
SOIC-20 surface mount package, and the 1 mm thin TSSOP-20
package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703




AD8804 pdf, 반도체, 판매, 대치품
AD8802/AD8804–Typical Performance Characteristics
1
0.75
0.5
VDD = +5V
VREFH = +5V
VREFL = 0V
0.25
0
–0.25
–0.5
–0.75
–1
0 32 64
TA = +85°C
TA = +25°C
TA = –40°C
96 128 160
CODE – Decimal
192 224 256
Figure 1. INL vs. Code
1
0.75
0.5
0.25
0
–0.25
–0.5
–0.75
–1
0
VDD = +5V
VREFH = +5V
VREFL = 0V
TA = +85°C
TA = +25°C
TA = –40°C
32 64 96 128 160 192 224 256
CODE – Decimal
Figure 2. Differential Nonlinearity Error vs. Code
1600
1280
960
VDD = +4.5V
VREF = +4.5V
VREFL = 0V
TA = +25°C
SS = 3600 PCS
640
320
0
0 0.2 0.4 0.6 0.8 1.0
ABSOLUTE VALUE TOTAL UNADJUSTED ERROR – LSB
Figure 3. Total Unadjusted Error Histogram
160
140
120
100
80
60
40
20
0
0
VDD = +5V
VREFH = +2V
VREFL = 0V
ONE DAC CHANGING WITH CODE,
OTHER DACs SET TO 00H
TA = +25°C
32 64
96 128 160 192 224
CODE – Decimal
256
Figure 4. Input Reference Current vs. Code
10k
1k
VDD = +5.5V
VREF = +5.5V
100
10
VDD = +2.7V
VREF = +2.7V
0
–55 –35 –15
5 25 45 65
TEMPERATURE – °C
85 105 125
Figure 5. Shutdown Current vs. Temperature
100k
10k
1k
VDD = +5.5V
VIN = +2.4V
100
10
1 VDD = +5.5V
VIN = +5.5V
0.1
0.01
0.001
–55 –35 –15
5 25 45 65
TEMPERATURE – °C
85 105 125
Figure 6. Supply Current vs. Temperature
–4– REV. 0

4페이지










AD8804 전자부품, 판매, 대치품
AD8802/AD8804
PROGRAMMING THE OUTPUT VOLTAGE
The output voltage range is determined by the external refer-
ence connected to VREFH and VREFL pins. See Figure 16 for a
simplified diagram of the equivalent DAC circuit. In the case of
the AD8802 its VREFL is internally connected to GND and
therefore cannot be offset. VREFH can be tied to VDD and VREFL
can be tied to GND establishing a basic rail-to-rail voltage out-
put programming range. Other output ranges are established by
the use of different external voltage references. The general
transfer equation which determines the programmed output
voltage is:
VO (Dx) = (Dx)/256 × (VREFH VREFL) + VREFL
Eq. 1
where Dx is the data contained in the 8-bit DACx register.
ladder, while the REFH reference is sourcing current into the
DAC ladder. The DAC design minimizes reference glitch cur-
rent maintaining minimum interference between DAC channels
during code changes.
DAC OUTPUTS (O1–O12)
The twelve DAC outputs present a constant output resistance of
approximately 5 kindependent of code setting. The distribu-
tion of ROUT from DAC-to-DAC typically matches within ± 1%.
However device-to-device matching is process lot dependent
having a ± 20% variation. The change in ROUT with temperature
has a 500 ppm/°C temperature coefficient. During power shut-
down all twelve outputs are open-circuited.
VREFH
TO OTHER DACS
P CH
N CH
DAC
REGISTER
D7
D6
D0
... ...
MSB
2R
OX
R
2R
R
...
LSB
2R
GND
VREFL
2R
Figure 16. AD8802/AD8804 Equivalent TrimDAC Circuit
For example, when VREFH = +5 V and VREFL = 0 V, the follow-
ing output voltages will be generated for the following codes:
D VOx
255 4.98 V
128 2.50 V
1 0.02 V
0 0.00 V
Output State
(VREFH = +5 V, VREFL = 0 V)
Full Scale
Half Scale (Midscale Reset Value)
1 LSB
Zero Scale
REFERENCE INPUTS (VREFH, VREFL)
The reference input pins set the output voltage range of all
twelve DACs. In the case of the AD8802 only the VREFH pin is
available to establish a user designed full-scale output voltage.
The external reference voltage can be any value between 0 and
VDD but must not exceed the VDD supply voltage. The AD8804
has access to the VREFL which establishes the zero-scale output
voltage, any voltage can be applied between 0 V and VDD. VREFL
can be smaller or larger in voltage than VREFH since the DAC
design uses fully bidirectional switches as shown in Figure 16.
The input resistance to the DAC has a code dependent variation
which has a nominal worst case measured at 55H, which is ap-
proximately 1.2 k. When VREFH is greater than VREFL, the
REFL reference must be able to sink current out of the DAC
CS
CLK
SDI
SHDN
AD8802/AD8804
D11
D10
D9
D8
D7
SER
REG
D D0
EN
ADDR
DEC
8
D7
DAC
REG
#1
D0
R
D7
DAC
REG
#12
D0
R
DAC
1
DAC
12
GND
RS VREFL
(AD8802 ONLY) (AD8804 ONLY)
Figure 17. Block Diagram
VDD
VREFH
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
DIGITAL INTERFACING
The AD8802/AD8804 contains a standard three-wire serial in-
put control interface. The three inputs are clock (CLK), CS and
serial data input (SDI). The positive-edge sensitive CLK input
requires clean transitions to avoid clocking incorrect data into
the serial input register. Standard logic families work well. If
mechanical switches are used for product evaluation, they
should be debounced by a flip-flop or other suitable means. Fig-
ure 17 block diagram shows more detail of the internal digital
circuitry. When CS is taken active low, the clock can load data
into the serial register on each positive clock edge, see Table II.
Table II. Input Logic Control Truth Table
CS CLK Register Activity
1X
0P
P1
No effect.
Shifts Serial Register One bit loading the next bit
in from the SDI pin.
Clock should be high when the CS returns to the
inactive state.
P = Positive Edge, X = Don’t Care.
The data setup and data hold times in the specification table
determine the data valid time requirements. The last 12 bits of
the data word entered into the serial register are held when CS
returns high. At the same time CS goes high it gates the address
decoder which enables one of the twelve positive-edge triggered
DAC registers, see Figure 18 detail.
REV. 0
–7–

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