|
|
PDF AD9501 Data sheet ( Hoja de datos )
| Número de pieza | AD9501 | |
| Descripción | Digitally Programmable Delay Generator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD9501 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
|
No Preview Available !
a
Digitally Programmable
Delay Generator
AD9501
FEATURES
Single 5 V Supply
FUNCTIONAL BLOCK DIAGRAM
TTL- and CMOS-Compatible
10 ps Delay Resolution
OFFSET
ADJUST RSET CEXT
2.5 ns to 10 s Full-Scale Range
Maximum Trigger Rate 50 MHz
APPLICATIONS
RESET
TRIGGER
TRIGGER
CIRCUIT
RAMP
GENERATOR
AD9501
–
Disk Drive Deskewing
Data Communications
Test Equipment
ORadar I and Q Matching
LATCH
D/A CONVERTER
TTL LATCHES
+
D7 D6 D5 D4 D3 D2 D1 D0
DAC GND GND +VS +VS
(MSB)
(LSB) OUTPUT
BSGENERAL DESCRIPTION
OThe AD9501 is a digitally programmable delay generator that
provides programmed time delays of an input pulse. Operating
Lfrom a single 5 V supply, the AD9501 is TTL- or CMOS-
Ecompatible and capable of providing accurate timing adjust-
ments with resolutions as low as 10 ps. Its accuracy and
TEprogrammability make it ideal for use in data deskewing and
pulse delay applications, as well as clock timing adjustments.
Full-scale delay range is set by the combination of an external
resistor and capacitor and can range from 2.5 ns to 10 ms for a
single AD9501. An 8-bit digital word selects a time delay within
the full-scale range. When triggered by the rising edge of an input
pulse, the output of the AD9501 will be delayed by an amount
equal to the selected time delay (tD) plus an inherent propaga-
tion delay (tPD).
The AD9501 is available for a commercial temperature range
of 0∞C to 70∞C in a 20-lead plastic DIP and a 20-lead plastic
leaded chip carrier (PLCC).
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
AD9501
THEORY OF OPERATION
The AD9501 is a digitally programmable delay device. Its func-
tion is to provide a precise incremental delay between input and
Figure 2 illustrates in detail how the delay is determined.
Minimum delay (tPD) is the sum of trigger circuit delay, ramp
generator delay, and comparator delay.
output, proportional to an 8-bit digital word applied to its delay
control port. Incremental delay resolution is 10 ps at the mini-
mum full-scale range of 2.5 ns. Digital delay data inputs, latch,
trigger, and reset are all TTL/CMOS-compatible. Output is
TTL-compatible.
The trigger circuit delay and comparator delay are fixed;
ramp generator delay is a variable affected by the rate of
change of the linear ramp and (to a lesser degree) the value of
the offset voltage described below.
Refer to the AD9501 Functional Block Diagram.
Maximum delay is the sum of minimum delay (tPD) and full-scale
program delay (tDFS).
Inside the unit, there are three main subcircuits: a linear ramp Ramp generator delay is the time required for the ramp to slew
generator, an 8-bit digital-to-analog converter (DAC), and a
from its reset voltage to the most positive DAC reference volt-
voltage comparator. The rising edge of the input (TRIGGER)
pulse initiates the delay cycle by triggering the ramp generator.
The voltage comparator monitors the ramp voltage and switches
the delayed output (Pin 10) HIGH when the ramp voltage crosses
the threshold set by the DAC output voltage. The DAC thresh-
old voltage is programmed by the user with digital inputs.
age (00H). The difference in these two voltages is nominally
18 mV (with OFFSET ADJUST open) or 34 mV (OFFSET
ADJUST grounded).
O TRIGGER
BSDELAYED OUTPUT
COMPARATOR
DELAY
ORESET
LETEDACREFERENCE
TRIGGER RAMP
CIRCUIT GEN.
DELAY DELAY
PROGRAMMED
DELAY
RESET PROP
DELAY (tRD)
LINEAR RAMP
SETTLING TIME
(tLRS)
(00H)
(tD)
PROGRAMMED
DAC THRESHOLD
(XXH)
RAMP GEN.
DELAY
DAC REFERENCE
(FFH)
PROGRAMMED
DELAY (tD)
FULL-SCALE
DELAY
RANGE
FULL–SCALE DELAY RANGE
(tD)
TRIGGER
INPUT
TRIGGER
GENERATOR
RAMP
GENERATOR
DAC
COMPARATOR
MINIMUM PROPAGATION DELAY = (tPD) = TRIGGER CIRCUIT DELAY + RAMP GENERATOR DELAY + COMPARATOR DELAY
MAXIMUM PROPAGATION DELAY = MINIMUM PROPAGATION DELAY (tPD) + FULL–SCALE RANGE (tDFS)
PROGRAMMED DELAY (tD) =
TOTAL DELAY = (tPD) + (tD)
DIGITAL VALUE
256
AD9501 TESTED WITH CEXT = 0 pF; RSET = 3.09 k⍀ (100 ns PROGRAMMED DELAY)
Figure 2. Internal Timing
REV. B
–5–
5 Page 
OUTLINE DIMENSIONS
20-Lead Plastic Dual In-Line Package [PDIP]
(N-20)
Dimensions shown in inches and (millimeters)
AD9501
0.985 (25.02)
0.965 (24.51)
0.945 (24.00)
20 11
0.295 (7.49)
0.285 (7.24)
0.275 (6.99)
1 10
0.325 (8.26)
0.310 (7.87)
0.180 (4.57)
MAX
0.015 (0.38) MIN
0.300 (7.62)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.100 0.060 (1.52) SEATING
(2.54)
BSC
0.050 (1.27)
PLANE
0.045 (1.14)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
O COMPLIANT TO JEDEC STANDARDS MO-095-AE
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
B (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
SOLETE20-Lead Plastic Leaded Chip Carrier [PLCC]
(P-20A)
Dimensions shown in inches and (millimeters)
0.048 (1.21)
0.042 (1.07)
0.056 (1.42)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
0.020
(0.50)
R
3
4
19
18
TOP VIEW
(PINS DOWN)
8
9
14
13
0.356 (9.04)
0.350 (8.89) SQ
0.050
(1.27)
BSC
0.395 (10.02)
0.385 (9.78)
SQ
0.180 (4.57)
0.165 (4.19)
0.20 (0.51)
MIN
0.020 (0.50)
R
0.021 (0.53)
0.013 (0.33)
0.330 (8.38)
0.032 (0.81) 0.290 (7.37)
0.026 (0.66)
0.120 (3.04)
0.090 (2.29)
0.040
0.025
(1.01)
(0.64)
R
BOTTOM
VIEW
(PINS UP)
COMPLIANT TO JEDEC STANDARDS MO-047AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
REV. B
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AD9501.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD9500 | Digitally Programmable Delay Generator | Analog Devices |
| AD9501 | Digitally Programmable Delay Generator | Analog Devices |
| AD9502 | Hybrid RS-170 Video Digitizer | Analog Devices |
| AD9508 | 1.65 GHz Clock Fanout Buffer | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |