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AD7541A 데이터시트 PDF




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부품번호 AD7541A 기능
기능 CMOS 12-Bit Monolithic Multiplying DAC
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AD7541A 데이터시트, 핀배열, 회로
a
CMOS
12-Bit Monolithic Multiplying DAC
AD7541A
FEATURES
Improved Version of AD7541
Full Four-Quadrant Multiplication
12-Bit Linearity (Endpoint)
All Parts Guaranteed Monotonic
TTL/CMOS Compatible
Low Cost
Protection Schottky Diodes Not Required
Low Logic Input Leakage
GENERAL DESCRIPTION
The Analog Devices AD7541A is a low cost, high performance
12-bit monolithic multiplying digital-to-analog converter. It is
fabricated using advanced, low noise, thin film on CMOS
technology and is available in a standard 18-lead DIP and in
20-terminal surface mount packages.
The AD7541A is functionally and pin compatible with the in-
dustry standard AD7541 device and offers improved specifica-
tions and performance. The improved design ensures that the
device is latch-up free so no output protection Schottky diodes
are required.
This new device uses laser wafer trimming to provide full 12-bit
endpoint linearity with several new high performance grades.
ORDERING GUIDE1
Model2
Temperature
Range
AD7541AJN 0°C to +70°C
AD7541AKN 0°C to +70°C
AD7541AJP 0°C to +70°C
AD7541AKP 0°C to +70°C
AD7541AKR 0°C to +70°C
AD7541AAQ –25°C to +85°C
AD7541ABQ –25°C to +85°C
AD7541ASQ –55°C to +125°C
AD7541ATQ –55°C to +125°C
AD7541ASE –55°C to +125°C
AD7541ATE –55°C to +125°C
Relative
Gain
Accuracy Error
TMIN to TMAX TA = +25؇C
± 1 LSB
± 1/2 LSB
± 1 LSB
± 1/2 LSB
± 1/2 LSB
± 1 LSB
± 1/2 LSB
± 1 LSB
± 1/2 LSB
± 6 LSB
± 1 LSB
±6
±1
±1
± 6 LSB
± 1 LSB
± 6 LSB
± 1 LSB
± 1 LSB
± 1/2 LSB
± 6 LSB
± 1 LSB
Package
Options3
N-18
N-18
P-20A
P-20A
R-18
Q-18
Q-18
Q-18
Q-18
E-20A
E-20A
NOTES
1Analog Devices reserves the right to ship either ceramic (D-18) or cerdip (Q-18)
hermetic packages.
2To order MIL-STD-883, Class B process parts, add /883B to part number. Contact
local sales office for military data sheet.
3E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip; R = Small Outline IC.
VREF
FUNCTIONAL BLOCK DIAGRAM
10k
10k
10k
20k
S1
20k
S2
20k
S3
20k
S12
20k
10k
BIT 1 (MSB) BIT 2
BIT 3
BIT 12 (LSB)
DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)
LOGIC: A SWITCH IS CLOSED TO IOUT1 FOR
ITS DIGITAL INPUT IN A "HIGH" STATE.
OUT2
OUT1
RFEEDBACK
PRODUCT HIGHLIGHTS
Compatibility: The AD7541A can be used as a direct replace-
ment for any AD7541-type device. As with the Analog Devices
AD7541, the digital inputs are TTL/CMOS compatible and
have been designed to have a ± 1 µA maximum input current
requirement so as not to load the driving circuitry.
Improvements: The AD7541A offers the following improved
specifications over the AD7541:
1. Gain Error for all grades has been reduced with premium
grade versions having a maximum gain error of ± 3 LSB.
2. Gain Error temperature coefficient has been reduced to
2 ppm/°C typical and 5 ppm/°C maximum.
3. Digital-to-analog charge injection energy for this new device
is typically 20% less than the standard AD7541 part.
4. Latch-up proof.
5. Improvements in laser wafer trimming provides 1/2 LSB max
differential nonlinearity for top grade devices over the operat-
ing temperature range (vs. 1 LSB on older 7541 types).
6. All grades are guaranteed monotonic to 12 bits over the
operating temperature range.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997




AD7541A pdf, 반도체, 판매, 대치품
AD7541A
GENERAL CIRCUIT INFORMATION
The simplified D/A circuit is shown in Figure 1. An inverted
R-2R ladder structure is used—that is, the binarily weighted
currents are switched between the OUT1 and OUT2 bus lines,
thus maintaining a constant current in each ladder leg indepen-
dent of the switch state.
VREF
10k
10k
10k
20k
20k
20k
20k
20k
S1 S2 S3
S12
10k
BIT 1 (MSB) BIT 2
BIT 3
BIT 12 (LSB)
DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)
LOGIC: A SWITCH IS CLOSED TO IOUT1 FOR
ITS DIGITAL INPUT IN A "HIGH" STATE.
OUT2
OUT1
RFEEDBACK
Figure 1. Functional Diagram (Inputs HIGH)
The input resistance at VREF (Figure 1) is always equal to RLDR
(RLDR is the R/2R ladder characteristic resistance and is equal to
value “R”). Since RIN at the VREF pin is constant, the reference
terminal can be driven by a reference voltage or a reference
current, ac or dc, of positive or negative polarity. (If a current
source is used, a low temperature coefficient external RFB is
recommended to define scale factor.)
EQUIVALENT CIRCUIT ANALYSIS
The equivalent circuits for all digital inputs LOW and all digital
inputs HIGH are shown in Figures 2 and 3. In Figure 2 with all
digital inputs LOW, the reference current is switched to OUT2.
The current source ILEAKAGE is composed of surface and junc-
tion leakages to the substrate, while the I/4096 current source
represents a constant 1-bit current drain through the termina-
tion resistor on the R-2R ladder. The ON capacitance of the
output N-channel switch is 200 pF, as shown on the OUT2
terminal. The OFF switch capacitance is 70 pF, as shown on
the OUT1 terminal. Analysis of the circuit for all digital inputs
HIGH, as shown in Figure 3 is similar to Figure 2; however, the
ON switches are now on terminal OUT1, hence the 200 pF at
that terminal.
RFB
R
ILEAKAGE
70pF
OUT1
VREF
R 15k
IREF
I/4096
ILEAKAGE
200pF
OUT2
Figure 2. DAC Equivalent Circuit All Digital Inputs LOW
VREF
R 15k
IREF
I/4096
ILEAKAGE
R
200pF
ILEAKAGE
70pF
RFB
OUT1
OUT2
Figure 3. DAC Equivalent Circuit All Digital Inputs HIGH
APPLICATIONS
UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)
Figure 4 shows the analog circuit connections required for uni-
polar binary (2-quadrant multiplication) operation. With a dc
reference voltage or current (positive or negative polarity) ap-
plied at Pin 17, the circuit is a unipolar D/A converter. With an
ac reference voltage or current, the circuit provides 2-quadrant
multiplication (digitally controlled attenuation). The input/
output relationship is shown in Table II.
R1 provides full-scale trim capability [i.e., load the DAC register
to 1111 1111 1111, adjust R1 for VOUT = –VREF (4095/4096)].
Alternatively, Full Scale can be adjusted by omitting R1 and R2
and trimming the reference voltage magnitude.
C1 phase compensation (10 pF to 25 pF) may be required for
stability when using high speed amplifiers. (C1 is used to cancel
the pole formed by the DAC internal feedback resistance and
output capacitance at OUT1).
Amplifier A1 should be selected or trimmed to provide VOS
10% of the voltage resolution at VOUT. Additionally, the ampli-
fier should exhibit a bias current which is low over the tempera-
ture range of interest (bias current causes output offset at VOUT
equal to IB times the DAC feedback resistance, nominally 11 k).
The AD544L is a high speed implanted FET input op amp with
low factory-trimmed VOS.
VDD R2*
16 18
VIN
VDD
RFB
OUT1 1
R1* 17 VREF AD7541A
OUT2 2
PINS 4–15
DGND
3
C1
33pF
VOUT
AD544L
(SEE TEXT)
BIT 1 – BIT 12
DIGITAL
GROUND
ANALOG
COMMON
*REFER TO TABLE 1
Figure 4. Unipolar Binary Operation
Table I. Recommended Trim Resistor Values vs. Grades
Trim
Resistor JN/AQ/SD KN/BQ/TD
R1
100
100
R2 47 33
Table II. Unipolar Binary Code Table for Circuit of Figure 4
Binary Number in DAC
MSB
LSB
Analog Output, VOUT
1111 1111 1111
1000 0000 0000
0000 0000
0000 0000
0001
0000
4095
–VIN  4096 
2048
–VIN  4096  = –1/2 VIN
1
–VIN  4096 
0 Volts
–4– REV. B

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AD7541A 전자부품, 판매, 대치품
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
AD7541A
20-Terminal Ceramic Leadless Chip Carrier
(E-20A)
0.100 (2.54)
0.064 (1.63)
0.200 (5.08)
0.075 BSC
(1.91)
REF
0.100 (2.54) BSC
0.358 (9.09) 0.358
0.342 (8.69)
SQ
(9.09)
MAX
SQ
0.095 (2.41)
0.075 (1.90)
0.011 (0.28)
0.007 (0.18)
R TYP
0.075 (1.91)
REF
19
18 20
3
4
1
BOTTOM
VIEW
14
13
8
9
0.015 (0.38)
MIN
0.028 (0.71)
0.022 (0.56)
0.050 (1.27)
BSC
45° TYP
0.088 (2.24)
0.055 (1.40) 0.150 (3.81)
0.054 (1.37)
0.045 (1.14)
BSC
20-Lead Plastic Leadless Chip Carrier
(P-20A)
0.048 (1.21)
0.042 (1.07)
0.056 (1.42)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
0.020
(0.50)
R
3 19
4 PIN 1 18
IDENTIFIER
TOP VIEW
(PINS DOWN)
8 14
9 13
0.356 (9.04)
0.350 (8.89) SQ
0.050
(1.27)
BSC
0.395 (10.02)
0.385 (9.78) SQ
0.180 (4.57)
0.165 (4.19)
0.025 (0.63)
0.015 (0.38)
0.021 (0.53)
0.013 (0.33) 0.330 (8.38)
0.032 (0.81) 0.290 (7.37)
0.026 (0.66)
0.040 (1.01)
0.025 (0.64)
0.110 (2.79)
0.085 (2.16)
18-Lead Plastic DIP
(N-18)
0.925 (23.49)
0.845 (21.47)
18 10
0.280 (7.11)
1 9 0.240 (6.10)
PIN 1
0.210
(5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
0.060 (1.52)
0.015 (0.38)
0.070 (1.77)
0.045 (1.15)
0.130
(3.30)
MIN
SEATING
PLANE
0.325 (8.25)
0.300 (7.62) 0.195 (4.95)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
18-Lead Cerdip
(Q-18)
0.005 (0.13) MIN
0.098 (2.49) MAX
18 10
0.310 (7.87)
0.220 (5.59)
19
PIN 1
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.960 (24.38) MAX
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.78) SEATING
0.030 (0.76) PLANE
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
15° 0.008 (0.20)
0°
18-Lead SOIC
(R-18)
0.4625 (11.75)
0.4469 (11.35)
18 10
19
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
x 45°
0.0098 (0.25)
0.0118 (0.30)
0.0040 (0.10)
0.0500 0.0192 (0.49)
(1.27) 0.0138 (0.35)
BSC
8°
SEATING 0.0125 (0.32) 0°
PLANE 0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
REV. B
–7–

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