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AD7846 데이터시트 PDF




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부품번호 AD7846 기능
기능 LC2MOS 16-Bit Voltage Output DAC
제조업체 Analog Devices
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AD7846 데이터시트, 핀배열, 회로
a
LC2MOS
16-Bit Voltage Output DAC
FEATURES
16-Bit Monotonicity over Temperature
؎2 LSBs Integral Linearity Error
Microprocessor Compatible with Readback Capability
Unipolar or Bipolar Output
Multiplying Capability
Low Power (100 mW Typical)
AD7846
FUNCTIONAL BLOCK DIAGRAM
VCC
VDD
VREF +
R
16
R
SEGMENT
SWITCH
MATRIX
VREF –
R
4
A2
A1
AD7846
R
R
12-BIT DAC
12
DAC LATCH
12
I/O LATCH
A3
CONTROL
LOGIC
RIN
VOUT
CS
R/ W
LDAC
CLR
GENERAL DESCRIPTION
The AD7846 is a 16-bit DAC constructed with Analog Devices’
LC2MOS process. It has VREF+ and VREF– reference inputs and
an on-chip output amplifier. These can be configured to give a
unipolar output range (0 V to +5 V, 0 V to +10 V) or bipolar
output ranges (± 5 V, ± 10 V).
The DAC uses a segmented architecture. The 4 MSBs in the
DAC latch select one of the segments in a 16-resistor string.
Both taps of the segment are buffered by amplifiers and fed to a
12-bit DAC, which provides a further 12 bits of resolution. This
architecture ensures 16-bit monotonicity. Excellent integral
linearity results from tight matching between the input offset
voltages of the two buffer amplifiers.
In addition to the excellent accuracy specifications, the AD7846
also offers a comprehensive microprocessor interface. There are
16 data I/O pins, plus control lines (CS, R/W, LDAC and CLR).
R/W and CS allow writing to and reading from the I/O latch.
This is the readback function which is useful in ATE applica-
tions. LDAC allows simultaneous updating of DACs in a multi-
DAC system and the CLR line will reset the contents of the
DAC latch to 00 . . . 000 or 10 . . . 000 depending on the state
of R/W. This means that the DAC output can be reset to 0 V in
both the unipolar and bipolar configurations.
The AD7846 is available in 28-lead plastic, ceramic, and PLCC
packages.
VSS
DB15 DB0
DGND
PRODUCT HIGHLIGHTS
1. 16-Bit Monotonicity
The guaranteed 16-bit monotonicity over temperature makes
the AD7846 ideal for closed-loop applications.
2. Readback
The ability to read back the DAC register contents minimizes
software routines when the AD7846 is used in ATE systems.
3. Power Dissipation
Power dissipation of 100 mW makes the AD7846 the lowest
power, high accuracy DAC on the market.
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000




AD7846 pdf, 반도체, 판매, 대치품
AD7846
ABSOLUTE MAXIMUM RATINGS1
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.4 V to +17 V
VCC to DGND . . . . . . . . . . . . . . . –0.4 V, VDD + 0.4 V or +7 V
(Whichever Is Lower)
VSS to DGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.4 V to –17 V
VREF+ to DGND . . . . . . . . . . . . . . . . VDD + 0.4 V, VSS – 0.4 V
VREF– to DGND . . . . . . . . . . . . . . . . VDD + 0.4 V, VSS – 0.4 V
VOUT to DGND2 . . . . . . . . VDD + 0.4 V, VSS – 0.4 V or ± 10 V
(Whichever Is Lower)
RIN to DGND . . . . . . . . . . . . . . . . . . VDD + 0.4 V, VSS – 0.4 V
Digital Input Voltage to DGND . . . . . . –0.4 V to VCC + 0.4 V
Digital Output Voltage to DGND . . . . . –0.4 V to VCC + 0.4 V
Power Dissipation (Any Package)
To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
Derates above +75°C . . . . . . . . . . . . . . . . . . . . . 10 mW/°C
Operating Temperature Range
J, K Versions . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
A, B Versions . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering) . . . . . . . . . . . . . . . . . . +300°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one Absolute
Maximum Rating may be applied at any one time.
2VOUT may be shorted to DGND, VDD, VSS, VCC provided that the power dissipation
of the package is not exceeded.
Model
AD7846JN
AD7846KN
AD7846JP
AD7846KP
AD7846AP
AD7846AQ
AD7846BP
Temperature Range
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
ORDERING GUIDE
Relative Accuracy
± 16 LSB
± 8 LSB
± 16 LSB
± 8 LSB
± 16 LSB
± 16 LSB
± 8 LSB
Package Description
Plastic DIP
Plastic DIP
Plastic Leaded Chip Carrier (PLCC)
Plastic Leaded Chip Carrier (PLCC)
Plastic Leaded Chip Carrier (PLCC)
Ceramic DIP
Plastic Leaded Chip Carrier (PLCC)
Package Options
N-28A
N-28A
P-28A
P-28A
P-28A
Q-28
P-28A
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electro-
static fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are removed.
WARNING!
ESD SENSITIVE DEVICE
TERMINOLOGY
LEAST SIGNIFICANT BIT
This is the analog weighting of 1 bit of the digital word in a DAC.
For the AD7846, 1 LSB = (VREF+ – VREF–)/216.
Relative Accuracy
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the end-
points of the DAC transfer function. It is measured after adjust-
ing for both endpoints (i.e., offset and gain errors are adjusted
out) and is normally expressed in least significant bits or as a
percentage of full-scale range.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal change between any two adjacent codes. A
specified differential nonlinearity of ± 1 LSB over the operating
temperature range ensures monotonicity.
Gain Error
Gain error is a measure of the output error between an ideal
DAC and the actual device output with all 1s loaded after offset
error has been adjusted out. Gain error is adjustable to zero
with an external potentiometer.
Offset Error
This is the error present at the device output with all 0s loaded
in the DAC. It is due to op amp input offset voltage and bias
current and the DAC leakage current.
Bipolar Zero Error
When the AD7846 is connected for bipolar output and 10 . . . 000
is loaded to the DAC, the deviation of the analog output from the
ideal midscale of 0 V is called the bipolar zero error.
Digital-to-Analog Glitch Impulse
This is the amount of charge injected from the digital inputs to
the analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-secs or nV-secs
depending upon whether the glitch is measured as a current or a
voltage.
Multiplying Feedthrough Error
This is an ac error due to capacitive feedthrough from either of
the VREF terminals to VOUT when the DAC is loaded with all 0s.
Digital Feedthrough
When the DAC is not selected (i.e., CS is held high), high fre-
quency logic activity on the digital inputs is capacitively coupled
through the device to show up as noise on the VOUT pin. This
noise is digital feedthrough.
–4– REV. E

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AD7846 전자부품, 판매, 대치품
4.0
TA = +25؇C
3.5 VREF+ = +5V
VREF= 0V
GAIN = +1
3.0
2.5
2.0
1.5
1.0
0.5
11
12 13
14 15
VDD/VSS Volts
16
Figure 13. Typical Linearity vs. VDD/VSS
1.0
TA = +25؇C
VREF+ = +5V
0.8 VREF= 0V
GAIN = +1
0.6
0.4
0.2
0
11 12 13
14 15 16
VDD/VSS Volts
Figure 14. Typical Monotonicity vs.
VDD/VSS
AD7846
CIRCUIT DESCRIPTION
Digital Section
Figure 15 shows the digital control logic and on-chip data
latches in the AD7846. Table II is the associated truth table.
The D/A converter has two latches that are controlled by four
signals: CS, R/W, LDAC and CLR. The input latch is con-
nected to the data bus (DB15–DB0). A word is written to the
input latch by bringing CS low and R/W low. The contents of
the input latch may be read back by bringing CS low and R/W
high. This feature is called “readback” and is used in system
diagnostic and calibration routines.
Data is transferred from the input latch to the DAC latch with
the LDAC strobe. The equivalent analog value of the DAC
latch contents appears at the DAC output. The CLR pin resets
the DAC latch contents to 000 . . . 000 or 100 . . . 000, depend-
ing on the state of R/W. Writing a CLR loads 000 . . . 000 and
reading a CLR loads 100 . . . 000. To reset a DAC to 0 V in a
unipolar system the user should exercise CLR while R/W is low;
to reset to 0 V in a bipolar system exercise the CLR while R/W
is high.
R/ W
CLR
Table II. Control Logic Truth Table
CS R/W LDAC CLR Function
1 XX
00X
01X
XX0
X0 X
X1 X
X 3-State DAC I/O Latch in High-
Z State
X DAC I/O Latch Loaded with
DB15–DB0
X Contents of DAC I/O Latch
Available on DB15–DB0
1 Contents of DAC I/O Latch
Transferred to DAC Latch
0 DAC Latch Loaded with
000 . . . 000
0 DAC Latch Loaded with
100 . . . 000
D/A Conversion
Figure 16 shows the D/A section of the AD7846. There are
three DACs, each of which have their own buffer amplifiers.
DAC1 and DAC2 are 4-bit DACs. They share a 16-resistor
string but have their own analog multiplexers. The voltage refer-
ence is applied to the resistor string. DAC3 is a 12-bit voltage
mode DAC with its own output stage.
DAC The 4 MSBs of the 16-bit digital code drive DAC1 and DAC2
while the 12 LSBs control DAC3. Using DAC1 and DAC2, the
16 MSBs select a pair of adjacent nodes on the resistor string and
DB15 RST
DB15 SET
DB14DB0
RST
DB15DB0
LATCHES
16
present that voltage to the positive and negative inputs of
LDAC DAC3. This DAC interpolates between these two voltages to
produce the analog output voltage.
To prevent nonmonotonicity in the DAC due to amplifier offset
voltages, DAC1 and DAC2 “leap-frog” along the resistor string.
3-STATE I/O
For example, when switching from Segment 1 to Segment 2,
CS
LATCH
DAC1 switches from the bottom of Segment 1 to the top of
16 Segment 2 while DAC2 stays connected to the top of Segment
DB15
DB0
Figure 15. Input Control Logic
1. The code driving DAC3 is automatically complemented to
compensate for the inversion of its inputs. This means that any
linearity effects due to amplifier offset voltages remain un-
changed when switching from one segment to the next and
16-bit monotonicity is ensured if DAC3 is monotonic. So,
12-bit resistor matching in DAC3 guarantees overall 16-bit
monotonicity. This is much more achievable than the 16-bit
matching which a conventional R-2R structure would have
needed.
REV. E
–7–

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