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PDF AD7849 Data sheet ( Hoja de datos )
| Número de pieza | AD7849 | |
| Descripción | 14-Bit/16-Bit DAC | |
| Fabricantes | Analog Devices | |
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FEATURES
14-bit/16-bit multiplying DAC
Guaranteed monotonicity
Output control on power-up and power-down internal or
external control
Versatile serial interface
DAC clears to 0 V in both unipolar and bipolar output ranges
APPLICATIONS
Industrial process controls
PC analog I/O boards
Instrumentation
GENERAL DESCRIPTION
The AD7849 is a 14-bit/16-bit serial input multiplying digital-
to-analog converter (DAC). The DAC architecture ensures
excellent differential linearity performance, and monotonicity is
guaranteed to 14 bits for the A grade and to 16 bits for all other
grades over the specified temperature ranges.
During power-up and power-down sequences (when the supply
voltages are changing), the VOUT pin is clamped to 0 V via a low
impedance path. To prevent the output of A3 from being shorted to
0 V during this time, Transmission Gate G1 is also opened. These
conditions are maintained until the power supplies stabilize,
and a valid word is written to the DAC register. At this time, G2
opens and G1 closes. Both transmission gates are also externally
controllable via the reset in (RSTIN) control input. For instance, if
the RSTIN input is driven from a battery supervisor chip, then
at power-off or during a brown out, the RSTIN input is driven
low to open G1 and close G2. The DAC must be reloaded, with
RSTIN high, to reenable the output. Conversely, the on-chip
voltage detector output (RSTOUT) is also available to the user
to control other parts of the system.
Serial Input,
14-Bit/16-Bit DAC
AD7849
VREF+
R
R
VREF–
R
FUNCTIONAL BLOCK DIAGRAM
VDD
VCC
R
A1 R
G1
10-BIT/
12-BIT
DAC
10/
12
A3
G2
LOGIC
CIRCUITRY
A2 DAC
LATCH
4
10/
12
VOLTAGE
MONITOR
AD7849
INPUT
LATCH
INPUT SHIFT REGISTER/
CONTROL LOGIC
ROFS
RST IN
VOUT
AGND
RST OUT
DGND SDIN SCLK SYNC CLR BIN/ DCEN SDOUT LDAC VSS
COMP
Figure 1.
The AD7849 has a versatile serial interface structure and can be
controlled over three lines to facilitate opto-isolator applications.
SDOUT is the output of the on-chip shift register and can be
used in a daisy-chain fashion to program devices in the multi-
channel system. The daisy-chain enable (DCEN) input controls
this function.
The BIN/COMP pin sets the DAC coding; with BIN/COMP set
to 0, the coding is straight binary; and with BIN/COMP set to 1,
the coding is twos complement. This allows the user to reset the
DAC to 0 V in both the unipolar and bipolar output ranges.
The part is available in a 20-lead PDIP package and a 20-lead SOIC
package.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©1995–2011 Analog Devices, Inc. All rights reserved.
1 page  
AD7849
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for design guidance and are no subject to test. VREF+ = 5 V; VDD = 14.25 V to 15.75 V; VSS = −14.25 V to
−15.75 V; VCC = 4.75 V to 5.25 V; ROFS connected to 0 V.
Table 3.
Parameter
DYNAMIC PERFORMANCE
Output Settling Time1
Slew Rate
Digital-to-Analog Glitch Impulse
AC Feedthrough
Digital Feedthrough
Output Noise Voltage Density, 1 kHz to 100 kHz
A, B, C Versions
7
10
4
250
150
1
5
80
Unit
μs typ
μs typ
V/μs typ
nV-sec typ
nV-sec typ
mV p-p typ
nV-sec typ
nV/√Hz typ
Test Conditions/Comments
To 0.006% FSR. VOUT loaded. VREF− = 0 V.
To 0.003% FSR. VOUT loaded. VREF− = −5 V.
DAC alternatively loaded with 00 … 00 and
111 … 11. VOUT loaded. LDAC permanently low.
BIN/COMP set to 1. VREF− = −5 V.
LDAC frequency = 100 kHz.
VREF− = 0 V, VREF+ = 1 V rms, 10 kHz sine wave.
DAC loaded with all 0s. BIN/COMP set to 0.
DAC alternatively loaded with all 1s and 0s.
SYNC high.
Measured at VOUT. VREF+ = VREF− = 0 V.
BIN/COMP set to 0.
1 LDAC = 0. Settling time does not include deglitching time of 5 μs (typical).
TIMING CHARACTERISTICS
VDD = 14.25 V to 15.75 V; VSS = −14.25 V to −15.75 V; VCC = 4.75 V to 5.25 V; RL = 2 kΩ, CL = 200 pF. All specifications TMIN to TMAX,
unless otherwise noted. Guaranteed by characterization. All input signals are specified tr = tf = 5 ns (10% to 90% of 5 V and timed from a
voltage level of 1.6 V.
Table 4.
Parameter
t1 1
t2
t3
t4
t5
t6 2
t7
tr
tf
Limit at 25°C (All Versions)
200
50
70
10
40
80
80
30
30
Limit at TMIN, TMAX (All Versions)
200
50
70
10
40
80
80
30
30
Unit
ns min
ns min
ns min
ns min
ns min
ns max
ns min
μs max
μs max
Test Conditions/Comments
SCLK cycle time
SYNC-to-SCLK setup time
SYNC-to-SCLK hold time
Data setup time
Data hold time
SCLK falling edge to SDO valid
LDAC, CLR pulse width
Digital input rise time
Digital input fall time
1 SCLK mark/space ratio range is 40/60 to 60/40.
2 SDO load capacitance is 50 pF.
Rev. C | Page 5 of 20
5 Page 
AD7849
CIRCUIT DESCRIPTION
DIGITAL-TO-ANALOG CONVERSION
Figure 15 shows the digital-to-analog section of the AD7849. There
are three on-chip DACs, each of which has its own buffer amplifier.
DAC1 and DAC2 are 4-bit DACs. They share a 16-resistor string,
but they have their own analog multiplexers. The voltage reference
is applied to the resistor string. DAC3 is a 12-bit voltage mode
DAC with its own output stage.
The four MSBs of the 16-bit digital input code drive DAC1 and
DAC2, while the 12 LSBs control DAC3. Using DAC1 and DAC2,
the MSBs select a pair of adjacent nodes on the resistor string
and present that voltage to the positive and negative inputs of
DAC3. This DAC interpolates between these two voltages to
produce the analog output voltage.
To prevent nonmonotonicity in the DAC due to amplifier offset
voltages, DAC1 and DAC2 leap-frog along the resistor string.
For example, when switching from Segment 1 to Segment 2, DAC1
switches from the bottom of Segment 1 to the top of Segment 2
while DAC 2 remains connected to the top of Segment 1. The
code driving DAC3 is automatically complemented to compensate
for the inversion of its inputs. This means that any linearity
effects due to amplifier offset voltages remain unchanged when
switching from one segment to the next, and 16-bit monotonicity is
ensured if DAC3 is monotonic. Therefore, 12-bit resistor matching
in DAC3 guarantees overall 16-bit monotonicity. This is much
more achievable than the 16-bit matching that a conventional
R-2R structure would need.
Output Stage
The output stage of the AD7849 is shown in Figure 14. It is capable
of driving a 2 kΩ load in parallel with 200 pF. The feedback and
offset resistors allow the output stage to be configured for gains of
1 or 2. Additionally, the offset resistor can be used to shift the
output range. The AD7849 has a special feature to ensure output
stability during power-up and power-down sequences. This feature
is available for control applications where actuators must not be
allowed to move in an uncontrolled fashion.
ROFS
R
10kΩ
R
10kΩ
G3
RSTIN
C1
G1
DAC 3
ONE-SHOT
LOGIC
CIRCUITRY
G2
VOUT
LDAC
VOLTAGE
MONITOR
Figure 14. Output Stage
AGND
RSTOUT
When the supply voltages are changing, the VOUT pin is clamped
to 0 V via a low impedance path. To prevent the output of A3
from being shorted to 0 V during this time, Transmission Gate G1
is opened. These conditions are maintained until the power
supplies stabilize, and a valid word is written to the DAC register.
At this time, G2 opens and G1 closes. Both transmission gates
are also externally controllable via the reset in (RSTIN) control
input. For instance, if the RSTIN input is driven from a battery
supervisor chip, then at power-off or during a brownout, the
RSTIN input will be driven low to open G1 and closeG2. The
DAC has to be reloaded, with RSTIN high, to reenable the output.
Conversely, the on-chip voltage detector output (RSTOUT) is
also available to the user to control other parts of the system.
The AD7849 output buffer is configured as a track-and-hold
amplifier. Although normally tracking its input, this amplifier
isplaced in hold mode for approximately 5 μs after the leading
edge of LDAC. This short state keeps the DAC output at its
previous voltage while the AD7849 is internally changing to its
new value. therefore, any glitches that occur in the transition are
not seen at the output. In systems where LDAC is permanently
low, deglitching is not in operation.
VREF+
VREF–
DAC 1
S1
S3
S15
S17
DB15 TO DB12
R
R DAC 2
S2
R
S4
A1
S14
R S16
R
R DB15 TO DB12
A2
Figure 15. Digital-to-Analog Conversion
DAC 3
10-BIT/12-BIT
DAC
10/12
OUTPUT
STAGE
Rev. C | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD7849.PDF ] | |
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