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부품번호 AD7853 기능
기능 3 V to 5 V Single Supply/ 200 kSPS 12-Bit Sampling ADCs
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AD7853 데이터시트, 핀배열, 회로
a
3 V to 5 V Single Supply, 200 kSPS
12-Bit Sampling ADCs
FEATURES
Specified for VDD of 3 V to 5.5 V
Read-Only Operation
AD7853–200 kSPS; AD7853L–100 kSPS
System and Self-Calibration with Autocalibration on
Power-Up
Low Power:
AD7853: 12 mW (VDD = 3 V)
AD7853L: 4.5 mW (VDD = 3 V)
Automatic Power Down After Conversion (25 W)
Flexible Serial Interface:
8051/SPI™/QSPI™/P Compatible
24-Lead DIP, SOIC and SSOP Packages
APPLICATIONS
Battery-Powered Systems (Personal Digital Assistants,
Medical Instruments, Mobile Communications)
Pen Computers
Instrumentation and Control Systems
High Speed Modems
AIN(+)
AIN(–)
REFIN/
REFOUT
CREF1
CREF2
CAL
AD7853/AD7853L*
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND AGND
T/H
2.5V
REFERENCE
BUF
AD7853/AD7853L
DVDD
DGND
COMP
CHARGE
REDISTRIBUTION
DAC
CALIBRATION
MEMORY
AND CONTROLLER
SAR + ADC
CONTROL
AMODE
CLKIN
CONVST
BUSY
SLEEP
GENERAL DESCRIPTION
The AD7853/AD7853L are high speed, low power, 12-bit
ADCs that operate from a single 3 V or 5 V power supply, the
AD7853 being optimized for speed and the AD7853L for low
power. The ADC powers up with a set of default conditions at
which time it can be operated as a read-only ADC. The ADC
contains self-calibration and system-calibration options to en-
sure accurate operation over time and temperature and have a
number of power-down options for low power applications.
The part powers up with a set of default conditions and can
operate as a read only ADC.
The AD7853 is capable of 200 kHz throughput rate while the
AD7853L is capable of 100 kHz throughput rate. The input
track-and-hold acquires a signal in 500 ns and features a pseudo-
differential sampling scheme. The AD7853/AD7853L voltage
range is 0 to VREF with both straight binary and twos comple-
ment output coding. Input signal range is to the supply, and the
part is capable of converting full power signals to 100 kHz.
CMOS construction ensures low power dissipation of typically
4.5 mW for normal operation and 1.15 mW in power-down
mode, with a throughput rate of 10 kSPS (VDD = 3 V). The part
is available in 24-lead, 0.3 inch wide dual-in-line package
(DIP), 24-lead small outline (SOIC) and 24-lead small shrink
outline (SSOP) packages.
SERIAL INTERFACE / CONTROL REGISTER
SM1 SM2 SYNC DIN DOUT SCLK POLARITY
PRODUCT HIGHLIGHTS
1. Specified for 3 V and 5 V supplies.
2. Automatic calibration on power-up.
3. Flexible power management options including automatic
power-down after conversion.
4. Operates with reference voltages from 1.2 V to VDD.
5. Analog input ranges from 0 V to VDD.
6. Self- and system calibration.
7. Versatile serial I/O port (SPI/QSPI/8051/µP).
8. Lower power version AD7853L.
*Patent pending.
SPI and QSPI are trademarks of Motorola, Incorporated.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998




AD7853 pdf, 반도체, 판매, 대치품
AD7853/AD7853L
TIMING SPECIFICATIONS1
(AVDD = DVDD = +3.0 V to +5.5
TMAX, unless otherwise noted)
V;
fCLKIN
=
4
MHz
for
AD7853
and
1.8/1
MHz
for
AD7853L;
TA
=
TMIN
to
Limit at TMIN, TMAX
(A, B Versions)
Parameter 5 V
3V
Units
Description
fCLKIN2
fSCLK3
t14
t2
tCONVERT
t3
t4
t55
t5A5
t65
t7
t8
t96
t106
t11
t11A
t127
t13
t148
t15
t16
tCAL9
tCAL19
tCAL29
500
4
1.8
1
4
fCLKIN
100
50
4.6
10 (18)
–0.4 tSCLK
ϯ0.4 tSCLK
0.6 tSCLK
50
50
75
40
20
0.4 tSCLK
0.4 tSCLK
30
30/0.4 tSCLK
50
50
90
50
2.5 tCLKIN
2.5 tCLKIN
31.25
27.78
3.47
500
4
1.8
1
4
fCLKIN
100
90
4.6
10 (18)
–0.4 tSCLK
ϯ0.4 tSCLK
0.6 tSCLK
90
90
115
60
30
0.4 tSCLK
0.4 tSCLK
50
50/0.4 tSCLK
50
50
130
90
2.5 tCLKIN
2.5 tCLKIN
31.25
kHz min
MHz max
MHz max
MHz max
MHz max
MHz max
ns min
ns max
µs max
µs max
ns min
ns min/max
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min/max
ns max
ns max
ns max
ns max
ns max
ns max
ms typ
27.78
ms typ
3.47 ms typ
Master Clock Frequency
L Version, 0°C to +70°C, B Grade Only
L Version, –40°C to +85°C
Interface Modes 1, 2, 3 (External Serial Clock)
Interface Modes 4, 5 (Internal Serial Clock)
CONVST Pulsewidth
CONVSTto BUSYPropagation Delay
Conversion Time = 18 tCLKIN
L Version 1.8 (1) MHz CLKIN. Conversion Time = 18 tCLKIN
SYNCto SCLKSetup Time (Noncontinuous SCLK Input)
SYNCto SCLKSetup Time (Continuous SCLK Input)
SYNCto SCLKSetup Time. Interface Mode 4 Only
Delay from SYNCuntil DOUT 3-State Disabled
Delay from SYNCuntil DIN 3-State Disabled
Data Access Time After SCLK
Data Setup Time Prior to SCLK
Data Valid to SCLK Hold Time
SCLK High Pulsewidth (Interface Modes 4 and 5)
SCLK Low Pulsewidth (Interface Modes 4 and 5)
SCLKto SYNCHold Time (Noncontinuous SCLK)
(Continuous SCLK) Does Not Apply to Interface Mode 3
SCLKto SYNCHold Time
Delay from SYNCuntil DOUT 3-State Enabled
Delay from SCLKto DIN Being Configured as Output
Delay from SCLKto DIN Being Configured as Input
CALto BUSYDelay
CONVSTto BUSYDelay in Calibration Sequence
Full Self-Calibration Time, Master Clock Dependent
(125013 tCLKIN)
Internal DAC Plus System Full-Scale Cal Time, Master Clock
Dependent (111114 tCLKIN)
System Offset Calibration Time, Master Clock Dependent
(13899 tCLKIN)
NOTES
Descriptions that refer to SCLK(rising) or SCLK(falling) edges here are with the POLARITY pin HIGH. For the POLARITY pin LOW then the opposite edge of
SCLK will apply.
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. See
Table X and timing diagrams for different interface modes and calibration.
2Mark/Space ratio for the master clock input is 40/60 to 60/40.
3For Interface Modes 1, 2, 3 the SCLK max frequency will be 4 MHz. For Interface Modes 4 and 5 the SCLK will be an output and the frequency will be f CLKIN.
4The CONVST pulsewidth will apply here only for normal operation. When the part is in power-down mode, a different CONVST pulsewidth will apply (see Power-
Down section).
5Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
6For self-clocking mode (Interface Modes 4, 5) the nominal SCLK high and low times will be 0.5 t SCLK = 0.5 tCLKIN.
7t12 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t 12, quoted in the timing characteristics is the true bus relin-
quish time of the part and is independent of the bus loading.
8t14 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true delay of the part
in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line knowing that a bus conflict will
not occur.
9The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to
the 1.8/1 MHz master clock.
Specifications subject to change without notice.
–4– REV. B

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AD7853 전자부품, 판매, 대치품
Pin Mnemonic
1 CONVST
2 BUSY
3 SLEEP
4 REFIN/
REFOUT
5 AVDD
6, 12 AGND
7 CREF1
8 CREF2
9 AIN(+)
10 AIN(–)
11 NC
13 AMODE
14 POLARITY
15 SM1
16 SM2
17 CAL
18 DVDD
19 DGND
20 DOUT
21 DIN
22 CLKIN
23 SCLK
24 SYNC
REV. B
PIN FUNCTION DESCRIPTIONS
AD7853/AD7853L
Description
Convert Start. Logic Input. A low to high transition on this input puts the track/hold into its hold mode and
starts conversion. When this input is not used, it should be tied to DVDD.
Busy Output. The busy output is triggered high by the falling edge of CONVST or rising edge of CAL, and
remains high until conversion is completed. BUSY is also used to indicate when the AD7853/AD7853L has
completed its on-chip calibration sequence.
Sleep Input/Low Power Mode. A Logic 0 initiates a sleep and all circuitry is powered down including the
internal voltage reference provided there is no conversion or calibration being performed. Calibration data
is retained. A Logic 1 results in normal operation. See Power-Down section for more details.
Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the
reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V and this appears
at the pin. This pin can be overdriven by an external reference or can be taken as high as AVDD. When this
pin is tied to AVDD, or when an externally applied reference approaches AVDD, the CREF1 pin should also be
tied to AVDD.
Analog Positive Supply Voltage, +3.0 V to +5.5 V.
Analog Ground. Ground reference for track/hold, reference and DAC.
Reference Capacitor (0.1 µF multilayer ceramic). This external capacitor is used as a charge source for the
internal DAC. The capacitor should be tied between the pin and AGND.
Reference Capacitor (0.01 µF ceramic disc). This external capacitor is used in conjunction with the on-chip
reference. The capacitor should be tied between the pin and AGND.
Analog Input. Positive input of the pseudo-differential analog input. Cannot go below AGND or above
AVDD at any time, and cannot go below AIN(–) when the unipolar input range is selected.
Analog Input. Negative input of the pseudo-differential analog input. Cannot go below AGND or above
AVDD at any time.
No Connect Pin.
Analog Mode Pin. This pin allows two different analog input ranges to be selected. A Logic 0 selects range
0 to VREF (i.e., AIN(+) – AIN(–) = 0 to VREF). In this case AIN(+) cannot go below AIN(–) and
AIN(–) cannot go below AGND. A Logic 1 selects range –VREF/2 to +VREF/2 (i.e., AIN(+) – AIN(–) =
–VREF/2 to +VREF/2). In this case AIN(+) cannot go below AGND so that AIN(–) needs to be biased to
+VREF/2 to allow AIN(+) to go from 0 V to +VREF V.
Serial Clock Polarity. This pin determines the active edge of the serial clock (SCLK). Toggling this pin will
reverse the active edge of the serial clock (SCLK). A Logic 1 means that the serial clock (SCLK) idles high
and a Logic 0 means that the serial clock (SCLK) idles low. It is best to refer to the timing diagrams and
Table IX for the SCLK active edges.
Serial Mode Select Pin. This pin is used in conjunction with the SM2 pin to give different modes of opera-
tion as described in Table X.
Serial Mode Select Pin. This pin is used in conjunction with the SM1 pin to give different modes of opera-
tion as described in Table X.
Calibration Input. This pin has an internal pull-up current source of 0.15 µA. A Logic 0 on this pin resets
all calibration control logic and initiates a calibration on its rising edge. There is the option of connecting a
10 nF capacitor from this pin to DGND to allow for an automatic self-calibration on power-up. This input
overrides all other internal operations. If the autocalibration is not required, this pin should be tied to a
logic high.
Digital Supply Voltage, +3.0 V to +5.5 V.
Digital Ground. Ground reference point for digital circuitry.
Serial Data Output. The data output is supplied to this pin as a 16-bit serial word.
Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can act
as an input pin or as a I/O pin depending on the serial interface mode the part is in (see Table X).
Master Clock Signal for the device (4 MHz for AD7853, 1.8 MHz for AD7853L). Sets the conversion and
calibration times.
Serial Port Clock. Logic input/output. The SCLK pin is configured as an input or output, dependent on the
type of serial data transmission (self-clocking or external-clocking) that has been selected by the SM1 and
SM2 pins. The SCLK idles high or low depending on the state of the POLARITY pin.
This pin can be an input level triggered active low (similar to a chip select in one case and to a frame sync
in the other) or an output (similar to a frame sync) pin depending on SM1, SM2 (see Table X).
–7–

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