Datasheet.kr   

AD7859 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD7859은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 AD7859 자료 제공

부품번호 AD7859 기능
기능 3 V to 5 V Single Supply/ 200 kSPS 8-Channel/ 12-Bit Sampling ADCs
제조업체 Analog Devices
로고 Analog Devices 로고


AD7859 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 28 페이지수

미리보기를 사용할 수 없습니다

AD7859 데이터시트, 핀배열, 회로
a
3 V to 5 V Single Supply, 200 kSPS
8-Channel, 12-Bit Sampling ADCs
AD7859/AD7859L*
FEATURES
Specified for VDD of 3 V to 5.5 V
AD7859–200 kSPS; AD7859L–100 kSPS
System and Self-Calibration
Low Power
Normal Operation
AD7859: 15 mW (VDD = 3 V)
AD7859L: 5.5 mW (VDD = 3 V)
Using Automatic Power-Down After Conversion (25 W)
AD7859: 1.3 mW (VDD = 3 V 10 kSPS)
AD7859L: 650 W (VDD = 3 V 10 kSPS)
Flexible Parallel Interface:
16-Bit Parallel/8-Bit Parallel
44-Pin PQFP and PLCC Packages
APPLICATIONS
Battery-Powered Systems (Personal Digital Assistants,
Medical Instruments, Mobile Communications)
Pen Computers
Instrumentation and Control Systems
High Speed Modems
GENERAL DESCRIPTION
The AD7859/AD7859L are high speed, low power, 8-channel,
12-bit ADCs which operate from a single 3 V or 5 V power
supply, the AD7859 being optimized for speed and the
AD7859L for low power. The ADC contains self-calibration
and system calibration options to ensure accurate operation over
time and temperature and have a number of power-down
options for low power applications.
The AD7859 is capable of 200 kHz throughput rate while the
AD7859L is capable of 100 kHz throughput rate. The input
track-and-hold acquires a signal in 500 ns and features a pseudo-
differential sampling scheme. The AD7859 and AD7859L input
voltage range is 0 to VREF (unipolar) and –VREF/2 to +VREF/2
about VREF/2 (bipolar) with both straight binary and 2s comple-
ment output coding respectively. Input signal range is to the
supply and the part is capable of converting full-power signals to
100 kHz.
CMOS construction ensures low power dissipation of typically
5.4 mW for normal operation and 3.6 µW in power-down mode.
The part is available in 44-pin, plastic quad flatpack package
(PQFP) and plastic lead chip carrier (PLCC).
AIN1
AIN8
REFIN/
REFOUT
CREF1
CREF2
CAL
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
AD7859/AD7859L
I/P
MUX
T/H
2.5V
REFERENCE
BUF
COMP
CHARGE
REDISTRIBUTION
DAC
CALIBRATION MEMORY
AND
CONTROLLER
SAR + ADC
CONTROL
PARALLEL INTERFACE/CONTROL REGISTER
DB15 – DB0
RD CS WR W/B
DVDD
DGND
CLKIN
CONVST
BUSY
SLEEP
PRODUCT HIGHLIGHTS
1. Operation with either 3 V or 5 V power supplies.
2. Flexible power management options including automatic
power-down after conversion.
3. By using the power management options a superior power
performance at slower throughput rates can be achieved.
AD7859: 1 mW typ @ 10 kSPS
AD7859L: 1 mW typ @ 20 kSPS
4. Operates with reference voltages from 1.2 V to the supply.
5. Analog input ranges from 0 V to VDD.
6. Self and system calibration.
7. Versatile parallel I/O port.
8. Lower power version AD7859L.
*Patent pending.
See page 28 for data sheet index.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703




AD7859 pdf, 반도체, 판매, 대치품
AD7859/AD7859L
TIMING SPECIFICATIONS1 (AVDD = DVDD = +3.0 V to +5.5 V; fCLKIN = 4 MHz for AD7859 and 1.8 MHz for AD7859L;
TA = TMIN to TMAX, unless otherwise noted)
Parameter 5 V
Limit at TMIN, TMAX
(A, B Versions)
3V
Units
Description
fCLKIN2
t13
t2
tCONVERT
t3
t4
t5
t6
t7
t84
t95
t10
t11
t12
t13
t14
t15
t16
t17
t184
t19
tCAL6
tCAL16
tCAL26
500
4
1.8
100
50
4.5
10
15
5
0
0
55
50
5
40
60
0
5
0
0
55
10
5
1/2 tCLKIN
2.5 tCLKIN
31.25
27.78
3.47
500
4
1.8
100
90
4.5
10
15
5
0
0
55
50
5
40
70
0
5
0
0
70
10
5
1/2 tCLKIN
2.5 tCLKIN
31.25
27.78
3.47
kHz min
MHz max
MHz max
ns min
ns max
µs max
µs max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns max
ms typ
ms typ
ms typ
Master Clock Frequency
L Version
CONVST Pulse Width
CONVST to BUSY Propagation Delay
Conversion Time = 18 tCLKIN
L Version 1.8 MHz CLKIN. Conversion Time = 18 tCLKIN
HBEN to RD Setup Time
HBEN to RD Hold Time
CS to RD to Setup Time
CS to RD Hold Time
RD Pulse Width
Data Access Time After RD
Bus Relinquish Time After RD
Bus Relinquish Time After RD
Minimum Time Between Reads
HBEN to WR Setup Time
HBEN to WR Hold Time
CS to WR Setup Time
CS to WR Hold Time
WR Pulse Width
Data Setup Time Before WR
Data Hold Time After WR
New Data Valid Before Falling Edge of BUSY
CS to BUSY in Calibration Sequence
Full Self-Calibration Time, Master Clock Dependent (125013
tCLKIN)
Internal DAC Plus System Full-Scale Cal Time, Master Clock
Dependent (111124 tCLKIN)
System Offset Calibration Time, Master Clock Dependent
(13889 tCLKIN)
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V.
2Mark/Space ratio for the master clock input is 40/60 to 60/40.
3The CONVST pulse width will here only apply for normal operation. When the part is in power-down mode, a different CONVST pulse width will apply (see Power-
Down section).
4Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
5t9 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 9, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
6The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to
the 1.8 MHz master clock.
Specifications subject to change without notice.
–4– REV. A

4페이지










AD7859 전자부품, 판매, 대치품
Mnemonic
CONVST
RD
WR
CS
REFIN/
REFOUT
AVDD
AGND
DVDD
DGND
CREF1
CREF2
AIN1–AIN8
W/B
DB0–DB7
DB8/HBEN
DB9–DB15
CLKIN
CAL
BUSY
SLEEP
NC
AD7859/AD7859L
Description
PIN FUNCTION DESCRIPTION
Convert Start. Logic input. A low to high transition on this input puts the track/hold into its hold
mode and starts conversion. When this input is not used, it should be tied to DVDD.
Read Input. Active low logic input. Used in conjunction with CS to read from internal registers.
Write Input. Active low logic input. Used in conjunction with CS to write to internal registers.
Chip Select Input. Active low logic input. The device is selected when this input is active.
Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the
reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V and this appears at the
pin. This pin can be overdriven by an external reference or can be taken as high as AVDD. When this pin is tied to
AVDD, then the CREF1 pin should also be tied to AVDD.
Analog Supply Voltage, +3.0 V to +5.5 V.
Analog Ground. Ground reference for track/hold, reference and DAC.
Digital Supply Voltage, +3.0 V to +5.5 V.
Digital Ground. Ground reference point for digital circuitry.
Reference Capacitor (0.1 µF multilayer ceramic). This external capacitor is used as a charge source for the inter-
nal DAC. The capacitor should be tied between the pin and AGND.
Reference Capacitor (0.01 µF ceramic disc). This external capacitor is used in conjunction with the on-chip refer-
ence. The capacitor should be tied between the pin and AGND.
Analog Inputs. Eight analog inputs which can be used as eight single ended inputs (referenced to AGND) or four
pseudo differential inputs. Channel configuration is selected by writing to the control register. None of the inputs
can go below AGND or above AVDD at any time. See Table III for channel selection.
Word/Byte input. When this input is at a logic 1, data is transferred to and from the AD7859/AD7859L in 16-bit
words on pins DB0 to DB15. When this pin is at a Logic 0, byte transfer mode is enabled. Data is transferred on
pins DB0 to DB7 and pin DB8/HBEN assumes its HBEN functionality.
Data Bits 0 to 7. Three state data I/O pins that are controlled by CS, RD and WR. Data output is straight binary
(unipolar mode) or twos complement (bipolar mode).
Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 7, a three state data I/O pin that is con-
trolled by CS, RD and WR. When W/B is low, this pin acts as the High Byte Enable pin. When HBEN is low,
then the low byte of data being written to or read from the AD7859/AD7859L is on DB0 to DB7. When HBEN
is high, then the high byte of data being written to or read from the AD7859/AD7859L is on DB0 to DB7.
Data Bits 9 to 15. Three state data I/O pins that are controlled by CS, RD and WR. Data output is straight bi-
nary (unipolar mode) or twos complement (bipolar mode).
Master Clock Signal for the device (4 MHz for AD7859, 1.8 MHz for AD7859L). Sets the conversion and calibra-
tion times.
Calibration Input. A logic 0 in this pin resets all logic. A rising edge on this pin initiates a calibration. This input
overrides all other internal operations.
Busy Output. The busy output is triggered high when a conversion or a calibration is initiated, and remains high
until the conversion or calibration is completed.
Sleep Input. This pin is used in conjunction with the PGMT0 and PGMT1 bits in the control register to deter-
mine the power-down mode. Please see the “Power-Down Options” section for details.
No connect pins. These pins should be left unconnected.
REV. A
–7–

7페이지


구       성 총 28 페이지수
다운로드[ AD7859.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
AD7851

14-Bit 333 kSPS Serial A/D Converter

Analog Devices
Analog Devices
AD7853

3 V to 5 V Single Supply/ 200 kSPS 12-Bit Sampling ADCs

Analog Devices
Analog Devices

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵