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AD7886 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD7886은 전자 산업 및 응용 분야에서
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부품번호 AD7886 기능
기능 LC2MOS 12-Bit/ 750 kHz/1 MHz/ Sampling ADC
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AD7886 데이터시트, 핀배열, 회로
a
LC2MOS
12-Bit, 750 kHz/1 MHz, Sampling ADC
AD7886
FEATURES
750 kHz/1 MHz Throughput Rate
1 s/750 ns Conversion Time
12-Bit No Missed Codes Over Temperature
67 dB SNR at 100 kHz Input Frequency
Low Power—250 mW typ
Fast Bus Access Time—57 ns max
APPLICATIONS
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
DSP Servo Control
GENERAL DESCRIPTION
The AD7886 is a 12-bit ADC with a sample-and-hold amplifier
offering high speed performance combined with low power dissi-
pation. The AD7886 is a triple pass flash ADC that uses 15
comparators in a 4-bit flash technique to achieve 12-bit accuracy
in 1 µs/750 ns conversion time. An on-chip clock oscillator pro-
vides the appropriate timing for each of the three conversion
stages, eliminating the need for any external clocks. Acquisition
time of the sample-and-hold amplifier gives a resulting through-
put rate of 750 kHz/1 MHz.*
The AD7886 operates from ± 5 V power supplies. Pin-strappable
inputs offer a choice of three analog input ranges: 0 V to 5 V,
0 V to 10 V or ± 5 V.
In addition to the traditional dc accuracy specifications such as
linearity, offset and full-scale errors, the AD7886 is also speci-
fied for dynamic performance parameters, including harmonic
distortion and signal-to-noise ratio.
The AD7886 has a high speed digital interface with three-state
data outputs. Conversion control is provided by a CONVST in-
put. Data access is controlled by CS and RD inputs, standard
microprocessor signals. The data access time of less than 57 ns
means that the AD7886 can interface directly to most modern
microprocessors, including DSP processors.
*Contact your local salesperson for further information on the 1 MHz
version.
FUNCTIONAL BLOCK DIAGRAM
VIN1
VIN2
+5REF
SUM
VREF
AGND
VDD
R3 R5
10k
R4
10k
R1
9k
3.5k
+
T/H
R2
6.3k
CLOCK
OSCILLATOR
AND TIMER
15
COMPARATORS
AND
4-BIT FLASH
LOGIC
4096
RESISTOR
DAC
SEGMENT SELECT
CS RD CONVST
CONTROL
TIMER
BUSY
4-BIT
LATCH
4-BIT
LATCH
4-BIT
LATCH
THREE
STATE
OUTPUTS
AD7886
DB11
DB0
VSS DGND
The AD7886 is fabricated in Analog Devices’ Linear Com-
patible CMOS process, a mixed technology process that
combines precision bipolar circuits with low power CMOS
logic.
The AD7886 is available in both a 28-pin DIP and a 28-pin
leaded chip carrier.
PRODUCT HIGHLIGHTS
1. Fast 1.33 µs/1 µs Throughput Time.
Fast throughput time makes the AD7886 suitable for a
wide range of data acquisition applications.
2. Dynamic Specifications for DSP Users.
The AD7886 is specified for ac parameters, including
signal-to-noise ratio, harmonic distortion and inter-
modulation distortion. Key digital timing parameters are
also tested and guaranteed over the full operating tem-
perature range.
3. Fast Microprocessor Interface.
Standard control signals, CS and RD, and fast bus ac-
cess times make the AD7886 easy to interface to micro-
processors.
4. Low Power.
LC2MOS fabrication process gives low power dissipa-
tion of 250 mW.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997




AD7886 pdf, 반도체, 판매, 대치품
AD7886
ORDERING GUIDE
Model1, 2
Temperature
Range
SNR
(dBs)
Integral
Nonlinearity
(LSBs)
Package
Option3
AD7886JD
AD7886KD
AD7886JP
AD7886KP
AD7886BD
AD7886TD
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–55°C to +125°C
65
67
65
67
67
65
± 2.0
± 2.0
± 2.0
± 2.0
D-28
D-28
P-28A2
P-28A2
D-28
D-28
NOTES
1Contact your sales office for availability of AD7886BD, AD7886TD and 1 MHz version.
2Analog Devices reserves the right to ship J-Leaded Ceramic Chip Carrier (JLCCC) in lieu of PLCC packages.
3D = Ceramic DIP; P = Plastic Leaded Chip Carrier.
PIN FUNCTION DESCRIPTION
DIP Pin
Number Mnemonic Description
Power Supply
10 & 19
15 & 24
16 & 23
VDD
VSS
AGND
5 DGND
Positive Power Supply, +5 V ± 5%. Both VDD pins must be tied together.
Negative Power Supply, –5 V ± 5%. Both VSS pins must be tied together.
Analog Ground. Both AGND pins must be tied together.
Digital Ground.
Analog and Reference Inputs
17 & 18 VIN
Analog Inputs, VIN1 and VIN2. The part can be pin strapped for any one of three analog input ranges;
20 +5REF
21 SUM
22 VREF
Interface and Control
1–4, DB7–DB4
6–9, DB3–DB0
25–28 DB11–DB8
11 BUSY
12 CS
13 RD
14 CONVST
Range
Pin Strap
Signal Input
0 V to 5 V
0 V to 10 V
±5 V
Connect VIN2 to VIN1
Connect VIN2 to GND
Connect VIN2 to +5 V
VIN1 & VIN2
VIN1
VIN1
+5 V Reference input. This input is used in conjunction with SUM and VREF inputs to scale an external
+5 V reference to –3.5 V, the required reference for the part (see Figure 2).
Summing Point. This input is used in conjunction with +5REF and VREF inputs to scale an external
+5 V reference to –3.5 V, the required reference for the part (see Figure 2).
Voltage Reference Input. The AD7886 is specified with VREF = –3.5 V.
Three-state data outputs.
These outputs are controlled by CS and RD. DB11 is the Most Significant Bit (MSB).
BUSY Output indicates converter status. BUSY is low during conversion.
Chip Select Input. The device is selected when this input is low.
Read Input. This active low signal, in conjunction with CS, is used to enable the output data three-state
drivers.
Conversion Start Input. This input is used to start conversion.
–4– REV. B

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AD7886 전자부품, 판매, 대치품
OFFSET AND GAIN ADJUSTMENT
In most digital signal processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can usually be eliminated in the analog domain by
ac coupling. Full-scale errors do not cause problems as long as
the input signal is within the full dynamic range of the ADC.
For applications requiring that the input signal range match the
full analog input dynamic range of the ADC, offset and full-
scale errors must be adjusted to zero.
UNIPOLAR OFFSET AND GAIN ERROR ADJUSTMENT
If absolute accuracy is an application requirement, offset and
gain can be adjusted to zero. Offset error must be adjusted be-
fore gain error. Zero offset is achieved by adjusting the offset of
the op amp driving the analog input (i.e., A1 in Figure 6). For
zero offset error, apply a voltage of 1 LSB to AIN and adjust
the op amp offset until the ADC output code flickers between
0000 0000 0000 and 0000 0000 0001.
0 V to 5 V Range: 1 LSB = 1.22 mV
0 V to 10 V Range: 1 LSB = 2.44 mV
For zero gain, error apply an analog input voltage equal to
FS–1 LSB (last code transition) at AIN and adjust R3 until the
ADC output code flickers between 1111 1111 1110 and 1111
1111 1111.
0 V to 5 V Range: FS–1 LSB = 4.99878 V
0 V to 10 V Range: FS–1 LSB = 9.99756 V
AIN
0 TO 5V
OR
0 TO 10V
AD845
+
A1
+ 5V
VIN1
VDD
VIN2**
+V
+VIN
VOUT
AD586
GND
+ 5V
R1
82k
R3
5k
AD707
– 3.5V
+
R2
56k
C1 C2
10µF
0.1µF
AGND
+ 5REF
SUM
VREF
AD7886*
VSS
– 5V
*ADDITIONAL PINS OMITTED FOR CLARITY
**0 TO 5V RANGE: CONNECT VIN2 TO VIN1
0 TO 10V RANGE: CONNECT VIN2 TO AGND
Figure 6. Unipolar Operation with Gain Error Adjust
AD7886
BIPOLAR OPERATION
Bipolar operation is achieved by providing a +10 V span on
the VIN1 input while offsetting the VIN2 input by +5 V. A
typical circuit is shown in Figure 7. The output code is off-
set binary. The ideal input/output transfer characteristic is
shown in Figure 8. The LSB size is (10/4096) V = 2.44 mV.
+ 5V
AIN
± 5V
+V
+VIN
VOUT + 5V
AD586
GND
VDD
VIN1
VIN2
AGND
+ 5REF
SUM
AD707
AD7886*
3.5V
VREF
+
C1
10µF
C2
0.1µF
VSS
– 5V
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 7. Bipolar Operation
OUTPUT
CODE
11...111
11...110
11...101
10...010
10...001
10...000
– FS +1LSB
2
01...111
01...110
01...101
00...001
–1LSB
+1LSB
+ FS – 1LSB
2
FS = 10V
1LSB =
FS
4096
00...000
VIN, INPUT VOLTAGE – LSBs
Figure 8. Ideal Input/Output Characteristics for
Bipolar Operation
REV. B
–7–

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