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AD7937 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD7937은 전자 산업 및 응용 분야에서
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부품번호 AD7937 기능
기능 LC2MOS 8+4 Loading Dual 12-Bit DAC
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AD7937 데이터시트, 핀배열, 회로
a
LC2MOS
(8+4) Loading Dual 12-Bit DAC
AD7937
FEATURES
Two 12-Bit DACs in One Package
DAC Ladder Resistance Matching: 0.5%
Surface-Mount Package
4-Quadrant Multiplication
Low Gain Error (3 LSB max Over Temperature)
Byte Loading Structure
Fast Interface Timing
APPLICATIONS
Automatic Test Equipment
Programmable Filters
Audio Applications
Synchro Applications
Process Control
GENERAL DESCRIPTION
The AD7937 contains two 12-bit current output DACs on one
monolithic chip. A separate reference input is provided for each
DAC. The dual DAC saves valuable board space, and the mono-
lithic construction ensures excellent thermal tracking. Both DACs
are guaranteed 12-bit monotonic over the full temperature range.
The AD7937 has a 2-byte (eight LSBs, four MSBs) loading
structure. It is designed for right-justified data format. The control
signals for register loading are A0, A1, CS, WR, and UPD. Data
is loaded to the input registers when CS and WR are low. To
transfer this data to the DAC registers, UPD must be taken
low with WR.
Added features on the AD7937 include an asynchronous CLR
line which is very useful in calibration routines. When this is
taken low, all registers are cleared. The double buffering of the
data inputs allows simultaneous update of both DACs. Also,
each DAC has a separate AGND line. This increases the device
versatility; for instance, one DAC may be operated with AGND
biased while the other is connected in the standard configuration.
The AD7937 is manufactured using the Linear Compatible
CMOS (LC2MOS) process. It is speed compatible with most
microprocessors and accepts TTL, 74HC, and 5 V CMOS logic
level inputs.
FUNCTIONAL BLOCK DIAGRAM
VDD
AD7937
UPD
A1
A0
CS
WR
CLR
CONTROL
LOGIC
DAC A MS
INPUT REG
DAC A LS
INPUT REG
48
DAC A REGISTER
12
DAC A
DAC B
12
DAC B REGISTER
48
DAC B MS
INPUT REG
DAC B LS
INPUT REG
IOUTA
AGNDA
RFBA
VREFA
VREFB
RFBB
IOUTB
AGNDB
DB7–DB0
DGND
PRODUCT HIGHLIGHTS
1. DAC-to-DAC Matching
Since both DACs are fabricated on the same chip, precise
matching and tracking is inherent. Many applications that are
not practical using two discrete DACs are now possible.
Typical matching: 0.5%.
2. Small Package Size
The AD7937 is packaged in a small 24-lead SOIC.
3. Wide Power Supply Tolerance
The device operates on a 5 V VDD, with ± 10% tolerance on
this nominal figure. All specifications are guaranteed over
this range.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000




AD7937 pdf, 반도체, 판매, 대치품
AD7937
Pin
1
2
3
4
5
6–11
13, 14
12
15
16
17
18
19
20
21
22
23
24
PIN FUNCTION DESCRIPTIONS
Mnemonic
AGNDA
IOUTA
RFBA
VREFA
CS
DB0–DB7
Description
Analog Ground for DAC A.
Current output terminal of DAC A.
Feedback resistor for DAC A.
Reference input to DAC A.
Chip Select Input Active low.
Eight data inputs, DB0–DB7.
DGND
A0
A1
CLR
WR
UPD
VDD
VREFB
RFBB
IOUTB
AGNDB
Digital Ground.
Address Line 0.
Address Line 1.
Clear Input. Active low. Clears all
registers.
Write Input. Active low.
Updates DAC Registers from inputs
registers.
Power supply input. Nominally 5 V to
15 V, with ± 10% tolerance.
Reference input to DAC B.
Feedback resistor for DAC B.
Current output terminal of DAC B.
Analog Ground for DAC B.
PIN CONFIGURATION
SOIC
AGNDA 1
24 AGNDB
IOUTA 2
23 IOUTB
RFBA 3
22 RFBB
VREFA
CS
DB0
DB1
4 21 VREFB
5 AD7937 20 VDD
6 TOP VIEW 19 UPD
7 (Not to Scale) 18 WR
DB2 8
17 CLR
DB3 9
16 A1
DB4 10
15 A0
DB5 11
14 DB7
DGND 12
13 DB6
CIRCUIT INFORMATION – D/A SECTION
The AD7937 contains two identical 12-bit multiplying D/A
converters. Each DAC consists of a highly stable R-2R ladder
and 12 N-channel current steering switches. Figure 2 shows a
simplified D/A circuit for DAC A. In the R-2R ladder, binary
weighted currents are steered between IOUTA and AGNDA. The
current flowing in each ladder leg is constant, irrespective of
switch state. The feedback resistor RFBA is used with an op amp
(see Figures 4 and 5) to convert the current flowing in IOUTA to
a voltage output.
VREFA
R
2R
S11
R
2R 2R 2R
S10 S0
RFBA
R
IOUTA
AGNDA
Figure 2. Simplified Circuit Diagram for DAC A
EQUIVALENT CIRCUIT ANALYSIS
Figure 3 shows the equivalent circuit for one of the D/A con-
verters (DAC A) in the AD7937. A similar equivalent circuit
can be drawn for DAC B.
R
RFBA
VREFA
IOUTA
R
D.VREF
R
RO
ILKG
COUT
AGNDA
Figure 3. Equivalent Analog Circuit for DAC A
COUT is the output capacitance due to the N-channel switches
and varies from about 50 pF to 100 pF with digital input code.
The current source ILKG is composed of surface and junction
leakages and approximately doubles every 10°C. RO is the equiva-
lent output resistance of the device which varies with input code.
DIGITAL CIRCUIT INFORMATION
The digital inputs are designed to be both TTL and 5 V CMOS
compatible. All logic inputs are static protected MOS gates with
typical input currents of less than 1 nA.
Table I. AD7937 Truth Table
CLR UPD CS WR A1 A0 Function
1 1 1 X X X No Data Transfer
1 1 X 1 X X No Data Transfer
0 X X X X X All Registers Cleared
1 1 0 0 0 0 DAC A LS Input Register
Loaded with DB7–DB0 (LSB)
1 1 0 0 0 1 DAC A MS Input Register
Loaded with DB3 (MSB)–DB0
1 1 0 0 1 0 DAC B LS Input Register
Loaded with DB7–DB0 (LSB)
1 1 0 0 1 1 DAC B MS Input Register
Loaded with DB3 (MSB)–DB0
1 0 1 0 X X DAC A, DAC B Registers
Updated Simultaneously from
Input Registers
1 0 0 0 X X DAC A, DAC B Registers are
Transparent
NOTE: X = Don’t care
–4– REV. 0

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AD7937 전자부품, 판매, 대치품
AD7937
APPLICATION HINTS
Output Offset: CMOS D/A converters in circuits such as Fig-
ures 4 and 5 exhibit a code-dependent output resistance which
in turn can cause a code-dependent error voltage at the output
of the amplifier. The maximum amplitude of this error, which
adds to the D/A converter nonlinearity, depends on VOS, where
VOS is the amplifier input offset voltage. To maintain specified
operation, it is recommended that VOS be no greater than
(25 ϫ 106) (VREF) over the temperature range of operation.
Suitable op amps are the AD711C and its dual version, the
AD712C. These op amps have a wide bandwidth and high slew
rate and are recommended for wide bandwidth ac applications.
AD711/AD712 settling time to 0.01% is typically 3 µs.
Temperature Coefficients: The gain temperature coefficient
of the AD7937 has a maximum value of 5 ppm/°C and typical
value of 1 ppm/°C. This corresponds to worst case gain shifts of
2 LSBs and 0.4 LSBs respectively over a 100°C temperature range.
When trim resistors R1 (R3) and R2 (R4) are used to adjust full
scale range as in Figure 4, the temperature coefficient of R1 (R3)
and R2 (R4) should also be taken into account.
High Frequency Considerations: AD7937 output capacitance
works in conjunction with the amplifier feedback resistance to
add a pole to the open-loop response. This can cause ringing or
oscillation. Stability can be restored by adding a phase compen-
sation capacitor in parallel with the feedback resistor. This is
shown as C1 and C2 in Figures 4 and 5.
Feedthrough: The dynamic performance of the AD7937 depends
upon the gain and phase stability of the output amplifier, together
with the optimum choice of PC board layout and decoupling
components.
MICROPROCESSOR INTERFACING
The byte loading structure of the AD7937 makes it very easy to
interface the device to any 8-bit microprocessor system. Figure
8 shows an example 8-bit interface between the AD7937 and a
generic 8-bit microcontroller/DSP processor. Pins D7 to D0 of
the processor are connected to pins D7 to D0 of the AD7937.
When writing to the DACs, the lower 8 bits must be written
first, followed by the upper four bits. The upper four bits should
be output on data lines D0 to D3.
CONTROLLER/
DSP PROCESSOR *
D7
DATA
BUS
D0
UPPER BITS
OF ADDRESS
BUS
FROM
SYSTEM
RESET
ADDRESS
DECODE
AD7937*
CLR
D7
D0
CS
UPD
A0
A1
R/W
*ADDITIONAL PINS OMITTED FOR CLARITY
A0
A1
WR
Figure 8. AD7937 8-Bit Interface
REV. 0
–7–

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