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PDF AD7938 Data sheet ( Hoja de datos )
| Número de pieza | AD7938 | |
| Descripción | 8-Channel/ 1.5 MSPS/ 12-Bit and 10-Bit Parallel ADCs with a Sequencer | |
| Fabricantes | Analog Devices | |
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Preliminary Technical Data
8-Channel, 1.5 MSPS, 12-Bit and 10-Bit
Parallel ADCs with a Sequencer
AD7938/AD7939
FEATURES
Fast throughput rate: 1.5 MSPS
Specified for VDD of 2.7 V to 5.25 V
Low power
8 mW max at 1.5 MSPS with 3 V supplies
16 mW max at 1.5 MSPS with 5 V supplies
8 analog input channels with a sequencer
Software configurable analog inputs
8-channel single-ended inputs
4-channel fully differential inputs
4-channel pseudo-differential inputs
7-channel pseudo-differential inputs
Accurate on-chip 2.5 V reference
Wide input bandwidth
70 dB SNR at 50 kHz input frequency
No pipeline delays
High speed parallel interface—word/byte modes
Full shutdown mode: 1 µA max
32-lead LFCSP and TQFP package
GENERAL DESCRIPTION
The AD7938/AD7939 are 12-bit and 10-bit, high speed, low
power, successive approximation (SAR) ADCs. The parts
operate from a single 2.7 V to 5.25 V power supply and feature
throughput rates up to 1.5 MSPS. The parts contain a low noise,
wide bandwidth, differential track-and-hold amplifier that can
handle input frequencies up to 20 MHz.
The AD7938/AD7939 feature eight analog input channels with
a channel sequencer that allow a preprogrammed selection of
channels to be converted sequentially. These parts can operate
with either single-ended, fully differential, or pseudo-
differential analog inputs.
The conversion process and data acquisition are controlled
using standard control inputs that allow easy interfacing with
microprocessors and DSPs. The input signal is sampled on the
falling edge of CONVST and the conversion is also initiated at
this point.
The AD7938/AD7939 have an accurate on-chip 2.5 V reference
that can be used as the reference source for the analog-to-digital
VREFIN/
VREFOUT
VIN0
VIN7
FUNCTIONAL BLOCK DIAGRAM
VDD
AGND
AD7938/AD7939
2.5V
VREF
I/P
MUX
T/H
12-/10-BIT
SAR ADC
AND
CONTROL
CLKIN
CONVST
BUSY
SEQUENCER
PARALLEL INTERFACE/CONTROL REGISTER
VDRIVE
DB0 DB11
CS RD WR W/B
Figure 1.
DGND
conversion. Alternatively, this pin can be overdriven to provide
an external reference.
These parts use advanced design techniques to achieve very low
power dissipation at high throughput rates. They also feature
flexible power management options. An on-chip control register
allows the user to set up different operating conditions,
including analog input range and configuration, output coding,
power management, and channel sequencing.
PRODUCT HIGHLIGHTS
1. High throughput with low power consumption.
2. Eight analog inputs with a channel sequencer.
3. Accurate on-chip 2.5 V reference.
4. Software configurable analog inputs. Single-ended, pseudo-
differential, or fully differential analog inputs that are
software selectable.
5. Single-supply operation with VDRIVE function. The VDRIVE
function allows the parallel interface to connect directly to
3 V, or 5 V processor systems independent of VDD.
6. No pipeline delay.
7. Accurate control of the sampling instant via a CONVST
input and once off conversion control.
Rev. PrN
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
AD7938/AD7939
AD7939—SPECIFICATIONS
VDD = VDRIVE = 2.7 V to 5.25 V, Internal/External VREF = 2.5V, unless otherwise noted, FCLKIN = 24 MHz, FSAMPLE = 1.5 MSPS; TA = TMIN to
TMAX, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)2
Signal-to-Noise Ratio (SNR)2
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second-Order Terms
Third-Order Terms
Channel to Channel Isolation
Aperture Delay2
Aperture Jitter2
Full Power Bandwidth2, 3
DC ACCURACY
Resolution
Integral Nonlinearity2
Differential Nonlinearity2
Total Unadjusted Error
Single-Ended and Pseudo-Differential Input
Offset Error2
Offset Error Match2
Gain Error2
Gain Error Match2
Fully Differential Input
Positive Gain Error2
Positive Gain Error Match2
Zero-Code Error2
Zero-Code Error Match2
Negative Gain Error2
Negative Gain Error Match2
ANALOG INPUT
Single-Ended Input Range
Pseudo-Differential Input Range: VIN+
VIN−
Fully Differential Input Range: VIN+ and VIN−
DC Leakage Current5
VIN+ and VIN−
Input Capacitance
REFERENCE INPUT/OUTPUT
VREF Input Voltage6
DC Leakage Current5
VREF Input Impedance
VREFOUT Output Voltage
VREFOUT Temperature Coefficient
VREF Noise
B Version1
60
60
−73
−73
−75
−75
−75
5
50
20
2.5
10
±0.5
±0.5
TBD
±4.5
±0.5
±2
±0.6
±2
±0.6
±3
±1
±2
±0.6
0 to VREF or 0 to 2 × VREF
0 to VREF or 2 × VREF
−0.1 to +0.4
VCM ± VREF/2
VCM ± VREF
±1
45
10
2.5
±1
10
2.5
15
10
130
Unit
dB min
dB min
dB max
dB max
dB typ
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
V
V
V
V
V
µA max
pF typ
pF typ
V
µA max
kΩ
V
ppm/°C typ
µV typ
µV typ
Test Conditions/Comments
FIN = 50 kHz sine wave
fa = 40.1 kHz, fb = 51.5 kHz
@ 3 dB
@ 0.1 dB
Guaranteed no missed codes to 10 bits
Straight binary output coding
Twos complement output coding
Depending on RANGE bit setting
Depending on RANGE bit setting
VCM = common-mode voltage4 = VREF/2
VCM = VREF, VIN+ or VIN− must remain within GND/VDD
When in track
When in hold
±1% for specified performance
±0.1% @ 25°C
0.1 Hz to 10 Hz bandwidth
0.1 Hz to 1 MHz bandwidth
Rev. PrN | Page 5 of 32
5 Page 
AD7938/AD7939
Preliminary Technical Data
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 . . .000) to
(00 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Offset Error Match
This is the difference in offset error between any two channels.
Gain Error
This is the deviation of the last code transition (111 . . .110) to
(111 . . . 111) from the ideal (i.e., VREF – 1 LSB) after the offset
error has been adjusted out.
Gain Error Match
This is the difference in gain error between any two channels.
Zero-Code Error
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to
+VREF biased about the VREFIN point. It is the deviation of the
mid scale transition (all 0s to all 1s) from the ideal VIN voltage,
i.e., VREF.
Zero-Code Error Match
This is the difference in zero-code error between any two
channels.
Positive Gain Error
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to
+VREF biased about the VREFIN point. It is the deviation of the last
code transition (011. . .110) to (011 .. . 111) from the ideal (i.e.,
+VREF − 1 LSB) after the zero-code error has been adjusted out.
Positive Gain Error Match
This is the difference in positive gain error between any two
channels.
Negative Gain Error
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to
+VREF biased about the VREF point. It is the deviation of the first
code transition (100 . . . 000) to (100 . . . 001) from the ideal (i.e.,
−VREFIN + 1 LSB) after the zero-code error has been adjusted
out.
Negative Gain Error Match
This is the difference in negative gain error between any two
channels.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale sine wave signal to all seven nonselected input channels
and applying a 50 kHz signal to the selected channel. The
channel-to-channel isolation is defined as the ratio of the power
of the 50 kHz signal on the selected channel to the power of the
noise signal that appears in the FFT of this channel.
Power Supply Rejection Ratio (PSRR)
PSRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the ADC VDD supply of frequency fS. The frequency
of the input varies from 1 kHz to 1 MHz.
PSRR (dB) = 10log(Pf/PfS)
Pf is the power at frequency f in the ADC output; PfS is the
power at frequency fS in the ADC output.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns into track mode at the
end of conversion. The track-and-hold acquisition time is the
time required for the output of the track-and-hold amplifier to
reach its final value, within ±1/2 LSB, after the end of
conversion.
Signal-to-(Noise + Distortion) Ratio (SINAD)
This is the measured ratio of signal-to-(noise + distortion) at
the output of the A/D converter. The signal is the rms amplitude
of the fundamental. Noise is the sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent on the number of quantization levels in
the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal-to-(noise +
distortion) ratio for an ideal N-bit converter with a sine wave
input is given by
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
Thus, for a 12-bit converter, this is 74 dB, and for a 10-bit
converter, this is 62 dB.
Rev. PrN | Page 11 of 32
11 Page | ||
| Páginas | Total 32 Páginas | |
| PDF Descargar | [ Datasheet AD7938.PDF ] | |
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