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AD607 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD607은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 AD607 자료 제공

부품번호 AD607 기능
기능 Low Power Mixer/AGC/RSSI 3 V Receiver IF Subsystem
제조업체 Analog Devices
로고 Analog Devices 로고


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AD607 데이터시트, 핀배열, 회로
a
FEATURES
Complete Receiver on a Chip: Monoceiver™ Mixer
–15 dBm 1 dB Compression Point
–8 dBm Input Third Order Intercept
500 MHz RF and LO Bandwidths
Linear IF Amplifier
Linear-in-dB Gain Control
MGC or AGC with RSSI Output
Quadrature Demodulator
On-Board Phase-Locked Quadrature Oscillator
Demodulates IFs from 400 kHz to 12 MHz
Can Also Demodulate AM, CW, SSB
Low Power
25 mW at 3 V
CMOS Compatible Power-Down
Interfaces to AD7013 and AD7015 Baseband Converters
APPLICATIONS
GSM, CDMA, TDMA, and TETRA Receivers
Satellite Terminals
Battery-Powered Communications Receivers
Low Power Mixer/AGC/RSSI
3 V Receiver IF Subsystem
AD607
PIN CONFIGURATION
20-Lead SSOP
(RS Suffix)
FDIN 1
20 VPS1
COM1 2
19 FLTR
PRUP 3
18 IOUT
LOIP 4
17 QOUT
RFLO 5 AD607 16 VPS2
RFHI
6
TOP VIEW
(Not to Scale)
15
DMIP
GREF 7
14 IFOP
MXOP 8
13 COM2
VMID 9
12 GAIN/RS
IFHI 10
11 IFLO
GENERAL DESCRIPTION
The AD607 is a 3 V low power receiver IF subsystem for opera-
tion at input frequencies as high as 500 MHz and IFs from
400 kHz to 12 MHz. It consists of a mixer, IF amplifiers, I and
Q demodulators, a phase-locked quadrature oscillator, AGC
detector, and a biasing system with external power-down.
The AD607’s low noise, high intercept mixer is a doubly-
balanced Gilbert cell type. It has a nominal –15 dBm input
referred 1 dB compression point and a –8 dBm input referred
third-order intercept. The mixer section of the AD607 also
includes a local oscillator (LO) preamplifier, which lowers the
required LO drive to –16 dBm.
The gain control input can serve as either a manual gain control
(MGC) input or an automatic gain control (AGC) voltage-
based RSSI output. In MGC operation, the AD607 accepts an
external gain-control voltage input from an external AGC detec-
tor or a DAC. In AGC operation, an onboard detector and an
external averaging capacitor form an AGC loop that holds the
IF output level at ± 300 mV. The voltage across this capacitor
then provides an RSSI output.
The I and Q demodulators provide inphase and quadrature
baseband outputs to interface with Analog Devices’ AD7013
(IS54, TETRA, MSAT) and AD7015 (GSM) baseband con-
verters. A quadrature VCO phase-locked to the IF drives the I
and Q demodulators. The I and Q demodulators can also de-
modulate AM; when the AD607’s quadrature VCO is phase
locked to the received signal, the in-phase demodulator becomes
a synchronous product detector for AM. The VCO can also be
phase-locked to an external beat-frequency oscillator (BFO),
and the demodulator serves as a product detector for CW or
SSB reception. Finally, the AD607 can be used to demodulate
BPSK using an external Costas Loop for carrier recovery.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703




AD607 pdf, 반도체, 판매, 대치품
AD607
Pin Mnemonic
1 FDIN
2 COM1
3 PRUP
4 LOIP
5 RFLO
6 RFHI
7 GREF
8 MXOP
9 VMID
10 IFHI
11 IFLO
12 GAIN/RSSI
13 COM2
14 IFOP
15 DMIP
16 VPS2
17 QOUT
18 IOUT
19 FLTR
20 VPS1
PIN DESCRIPTION
Reads
Frequency Detector Input
Common #1
Power-Up Input
Local Oscillator Input
RF “Low” Input
RF “High” Input
Gain Reference Input
Mixer Output
Midsupply Bias Voltage
IF “High” Input
IF “Low” Voltage
Gain Control Input/RSSI Output
Common #2
IF Output
Demodulator Input
VPOS Supply #2
Quadrature Output
In-Phase Output
PLL Loop Filter
VPOS Supply #1
Function
PLL input for I/Q demodulator quadrature oscillator, ± 400 mV
drive required from external oscillator. Must be biased at VP/2.
Supply common for RF front end and main bias.
3 V/5 V CMOS compatible power-up control; logical high =
powered-up; max input level = VPS1 = VPS2.
LO input, ac coupled ± 54 mV LO input required (–16 dBm for
50 input termination).
Usually connected to ac ground.
AC coupled, ± 56 mV, max RF input for linear operation.
High impedance input, typically 1.5 V, sets gain scaling.
High impedance, single-sided current output, ± 1.3 V max voltage
output (± 6 mA max current output).
Output of the midsupply bias generator (VMID = VPOS/2).
AC coupled IF input, ± 56 mV max input for linear operation.
Reference node for IF input; auto-offset null.
High impedance input, 0 V–2 V using 3 V supply, max gain at
V = 0. RSSI Output when using Internal AGC Detector; RSSI
voltage is across AGC Capacitor connected to this pin.
Supply common for IF stages and demodulator.
Low impedance, single-sided voltage output, +5 dBm (± 560 mV)
max.
Signal input to I and Q demodulators ± 150 mV max input at IF
> 3 MHz for linear operation; ± 75 mV max input at IF < 3 MHz
for linear operation. Must be biased at VP/2.
Supply to high-level IF, PLL, and demodulators.
Low impedance Q baseband output ± 1.23 V full scale in 20 k
min load; ac coupled.
Low impedance I baseband output; ± 1.23 V full scale in 20 k
min load; ac coupled.
Series RC PLL Loop filter, connected to ground.
Supply to mixer, low level IF, PLL, and gain control.
PIN CONNECTION
20-Pin SSOP (RS-20)
FDIN 1
20 VPS1
COM1 2
19 FLTR
PRUP 3
18 IOUT
LOIP 4
17 QOUT
RFLO 5 AD607 16 VPS2
RFHI
6
TOP VIEW
(Not to Scale)
15
DMIP
GREF 7
14 IFOP
MXOP 8
13 COM2
VMID 9
12 GAIN/RS
IFHI 10
11 IFLO
–4– REV. 0

4페이지










AD607 전자부품, 판매, 대치품
REV. 0
HP6633A
VPOS
IEEE
VNEG
SPOS
SNEG
DCPS
DP8200
VPOS
IEEE
VNEG
SPOS
SNEG
VREF
HP34401A
HI
GPIB
DMM
LO
I
R1
499k
CHARACTERIZATION
BOARD
RFHI
LOIP
RX
L
MXOP
IFHI IFOP
DMIP
FDIN
PLL
IOUT
QOUT
VPOS
PRUP
GAIN
BIAS
Figure 5. GAIN Pin Bias Test Set
HP6633A
VPOS
IEEE
VNEG
SPOS
SNEG
DCPS
DP8200
VPOS
IEEE
VNEG
SPOS
SNEG
VREF
HP34401A
HI
GPIB
DMM
LO
I
R1
499k
CHARACTERIZATION
BOARD
RFHI
LOIP
RX
L
MXOP
IFHI IFOP
DMIP
FDIN
PLL
IOUT
QOUT
VPOS
PRUP
GAIN
BIAS
Figure 6. Demodulator Bias Test Set
HP3325B
IEEE
RF_OUT
SYNTHESIZER
HP6633A
VPOS
IEEE
VNEG
SPOS
SNEG
DCPS
HP6633A
VPOS
IEEE
VNEG
SPOS
SNEG
DCPS
HP34401A
HI
GPIB
DMM
LO
I
R1
10k
CHARACTERIZATION
BOARD
RFHI
LOIP
MXOP
RX
L
IFHI IFOP
DMIP
FDIN
PLL
IOUT
QOUT
VPOS
PRUP
GAIN
BIAS
HP8594E
RF_IN
IEEE
SPEC AN
Figure 7. Power-Up Threshold Test Set
–7–
AD607

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