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PDF AD608 Data sheet ( Hoja de datos )
| Número de pieza | AD608 | |
| Descripción | Low Power Mixer/Limiter/RSSI 3 V Receiver IF Subsystem | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Low Power Mixer/Limiter/RSSI
3 V Receiver IF Subsystem
AD608
FEATURES
Mixer
−15 dBm, 1 dB compression point
−5 dBm IP3
24 dB conversion gain
>500 MHz input bandwidth
Logarithmic/limiting amplifier
80 dB RSSI range
±3° phase stability over 80 dB range
Low power
21 mW at 3 V power consumption
CMOS-compatible power-down to 300 μW typical
200 ns enable/disable time
APPLICATIONS
PHS, GSM, TDMA, FM, or PM receivers
Battery-powered instrumentation
Base station RSSI measurements
GENERAL DESCRIPTION
The AD608 provides a low power, low distortion, low noise mixer
as well as a complete, monolithic logarithmic/limiting amplifier
that uses a successive-detection technique. In addition, the AD608
provides both a high speed received signal strength indicator
(RSSI) output with 80 dB dynamic range and a hard-limited
output. The RSSI output is from a two-pole postdemodulation
low-pass filter and provides a loadable output voltage of 0.2 V to
1.8 V. The AD608 operates from a single 2.7 V to 5.5 V supply
at a typical power level of 21 mW at 3 V.
The RF and local oscillator (LO) bandwidths both exceed
500 MHz. In a typical IF application, the AD608 can accept the
output of a 240 MHz surface acoustic wave (SAW) filter and down-
convert it to a nominal 10.7 MHz IF with a conversion gain of
24 dB (ZIF = 165 Ω). The AD608 logarithmic/limiting amplifier
section handles any IF from low frequency (LF) up to 30 MHz.
The mixer is a doubly balanced gilbert-cell mixer and operates
linearly for RF inputs spanning −95 dBm to −15 dBm. It has a
nominal −5 dBm third-order intercept. An on-board LO pre-
amplifier requires only −16 dBm of LO drive. The current output
of the mixer drives a reverse-terminated, industry-standard
10.7 MHz, 330 Ω filter.
The nominal logarithmic scaling is such that the output is +0.2 V
for a sinusoidal input to the IF amplifier of −75 dBm and +1.8 V
at an input of +5 dBm; over this range, the logarithmic confor-
mance is typically ±1 dB. The logarithmic slope is proportional
to the supply voltage. A feedback loop automatically nulls the
input offset of the first stage down to the submicrovolt level.
The AD608 limiter output provides a hard-limited signal output
at 400 mV p-p. The voltage gain of the limiting amplifier to this
output is more than 100 dB. Transition times are 11 ns and the
phase is stable to within ±3° at 10.7 MHz for signals from −75 dBm
to +5 dBm.
The AD608 is enabled by a CMOS logic-level voltage input,
with a response time of 200 ns. When disabled, the standby
power is reduced to 300 μW within 400 ns.
The AD608 is specified for the industrial temperature range of
−25°C to +85°C for 2.7 V to 5.5 V supplies and −40°C to +85°C for
3.0 V to 5.5 V supplies. This device comes in a 16-lead plastic SOIC.
24dB MIXER GAIN
FUNCTIONAL BLOCK DIAGRAM
3dB NOMINAL
INSERTION LOSS
110dB LIMITER GAIN
90dB RSSI
RFHI
RF INPUT
–95dBm TO
–15dBm1
5
RFLO 6
±6mA MAX OUTPUT
(±890mV INTO 165Ω)
MIXER
LO
PREAMP
MXOP
7
BPF
DRIVER
VMID
8
MIDSUPPLY
IF BIAS
BIAS
IF INPUT
–75dBm TO
+15dBm2
10.7MHz
BAND-PASS
FILTER
IFHI
9
330Ω
100nF
330Ω
10nF
+
100Ω
10
IFLO
18nF
13
FDBK
VPS1 COM1 LOHI COM2
PRUP
1 23
4 16
2.7V TO
5.5V
LO INPUT
–16dBm
CMOS LOGIC
INPUT
1–15dBm = ±56mV MAXIMUM FOR LINEAR OPERATION.
239.76µV RMS TO 397.6mV RMS FOR ±1dB RSSI ACCURACY.
Figure 1.
7 FULL-WAVE
RECTIFIER CELLS
5-STAGE IF AMPLIFIER
(16dB PER STAGE)
2MHz
LPF
RSSI
11
RSSI OUTPUT
20mV/dB
0.2V TO 1.8V
COM3 12
VPS2 14 +2.7V TO 5.5V
LMOP
15 LIMITER
OUTPUT
FINAL
400mV p-p
LIMITER
AD608
±50µA
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©1996–2009 Analog Devices, Inc. All rights reserved.
1 page  
AD608
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltages VPS1, VPS2
Internal Power Dissipation
Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 60 sec)
Rating
+6 V
600 mW
−40°C to +85°C
−65°C to +150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3.
Package Type
16-Lead SOIC
θJA Unit
110 °C/W
ESD CAUTION
Rev. C | Page 4 of 16
5 Page 
AD608
IF FILTER TERMINATIONS
The AD608 was designed to drive a parallel-terminated 10.7 MHz
band-pass filter (BPF) with a 330 Ω impedance. With a 330 Ω
parallel-terminated filter, Pin MXOP sees a 165 Ω termination,
and the gain is nominally 24 dB. Other filter impedances and
gains can be accommodated by either accepting an increase or
decrease in gain in proportion to the filter impedance or by
keeping the impedance seen by MXOP at a nominal 165 Ω (by
using resistive dividers or matching networks). Figure 23 shows a
simple resistive voltage divider for matching an assortment of
filter impedances, and Table 6 lists component values.
THE LOGARITHMIC IF AMPLIFIER
The logarithmic IF amplifier consists of five amplifier stages
of 16 dB gain each, plus a final limiter. The IF bandwidth is
30 MHz (−1 dB), and the limiting gain is 110 dB. The phase
skew is ±3° from −75 dBm to +5 dBm (approximately 111 μV p-p
to 1.1 V p-p). The limiter output impedance is 200 Ω, and the
limiter output drive is ± 200 mV (400 mV p-p) into a 5 kΩ load.
In the absence of an input signal, the limiter output limits noise
fluctuations, producing an output that continues to swing
400 mV p-p, but with random zero crossings.
OFFSET FEEDBACK LOOP
Because the logarithmic amplifier is dc-coupled and has more
than 110 dB of gain from the input to the limiter output, a dc
offset at its input of even a few microvolts causes the output to
saturate. Therefore, the AD608 uses a low frequency feedback
loop to null the input offset. Referring to Figure 23, the loop
consists of a current source driven by the limiter, which sends
50 μA current pulses to Pin FDBK. The pulses are low-pass filtered
by a π-network consisting of C1, R4, and C5. The smoothed dc
voltage that results is subtracted from the input to the IF amplifier
at Pin IFLO. Because this is a high gain amplifier with a feedback
loop, care should be taken in layout and component values to
prevent oscillation. Recommended values for the common IFs
of 450 kHz, 455 kHz, 6.5 MHz, and 10.7 MHz are listed in Table 6.
24dB MIXER GAIN
12dB NOMINAL
INSERTION LOSS
(ASSUMES 6dB IN FILTER)
110dB LIMITER GAIN
90dB RSSI
RFHI 5
RFLO 6
MIXER
LO
PREAMP
MXOP
7
BPF
DRIVER
VMID
8
MIDSUPPLY
IF BIAS
BIAS
BAND-PASS
FILTER
R2
R1 R3
C5
100nF +
R4
C1
VPS1 COM1
12
5V
C1
1µF
LOHI COM2 PRUP
3 4 16
C2
100pF
47kΩ
IFHI
9
10
IFLO
13
FDBK
7 FULL-WAVE
RECTIFIER CELLS
2MHz
LPF
5-STAGE IF AMPLIFIER
(16dB PER STAGE)
FINAL
LIMITER
11 RSSI
12 COM3
14 VPS2
15 LMOP
AD608
±50µA
LO INPUT
–16dBm
CMOS LOGIC
INPUT
Figure 23. Applications Diagram for Common IFs and Filter Impedances
Table 6. AD608 Filter Termination and Offset-Null Feedback Loop Resistor and Capacitor Values for Common IFs
IF
450 kHz2
455 kHz
6.5 MHz
10.7 MHz
Filter Impedance
1500 Ω
1500 Ω
1000 Ω
330 Ω
Filter Termination Resistor
Values1 for 24 dB of Mixer Gain
R1 R2 R3
174 Ω
1330 Ω
1500 Ω
174 Ω
1330 Ω
1500 Ω
178 Ω
825 Ω
1000 Ω
330 Ω
0Ω
330 Ω
R4
1000 Ω
1000 Ω
100 Ω
100 Ω
Offset-Null
Feedback Loop Values
C1 C5
200 nF
100 nF
200 nF
100 nF
18 nF
10 nF
18 nF
10 nF
1 Resistor values were calculated so that R1 + R2 = ZFILTER and R1||(R2 + ZFILTER) = 165 Ω.
2 Operation at IFs of 450 kHz and 455 kHz requires use of an external low-pass filter with at least one pole at a cutoff frequency of 90 kHz (a decade below the ripple at 900 kHz).
Rev. C | Page 10 of 16
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet AD608.PDF ] | |
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