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부품번호 AD6402 기능
기능 IF Transceiver Subsystem
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AD6402 데이터시트, 핀배열, 회로
a
IF Transceiver Subsystem
AD6402
FEATURES
On-Chip Regulator
PLL Demodulator
On-Chip VCO
No Trims
Excellent Sensitivity
28-Lead SSOP Package
APPLICATIONS
DECT/PWT/WLAN
TDMA FM/FSK Systems
GENERAL DESCRIPTION
The AD6402 is a complete transceiver subsystem for use in
high bit rate radio systems employing FM or FSK modulation.
It is optimized for use in time domain multiple access (TDMA)
systems with communications rates of approximately 1 MBPS.
The AD6402 integrates key functions, including VCOs and a
low drop-out voltage regulator. The AD6402 operates directly
from an unregulated battery supply of 3.1 V to 4.5 V and pro-
vides a regulated voltage output which can be used for VCO
supply regulation on a companion RF chip such as the AD6401.
The AD6402 transceiver consists of a mixer, integrated IF
bandpass filter, IF limiter with RSSI detection, VCO, PLL
demodulator and a low dropout voltage regulator. On receive, it
downconverts an IF signal in the 110 MHz range to a second
IF frequency, this frequency being determined by the demodu-
lator reference divide ratios. It then filters, amplifies, and de-
modulates this signal. The AD6402 provides a filtered baseband
FUNCTIONAL BLOCK DIAGRAM
IFIN
TXOUT
TXOUTB
VCO
LIMITER/FILTER
PLL
DEMOD
2
AD6402
IF
VCO
VOLTAGE
REGULATOR
MODE
CONTROL
VREF
1
DC
OFFSET
COMP
RSSI
CFILT
DOUT
DFILP
PLLOUT
REFSEL
COFF
REFIN
FMMOD2
FMMOD1
VREG VBATT SLREF CTL1...3
MODOUT
data output. On transmit, it accepts a Gaussian Frequency Shift
Keying (GFSK) baseband signal, low-pass filters the signal if
required using the on-chip op amp and modulates the IF VCO
by varying the bias voltage on an off-chip varactor diode used in
the tank circuit.
The AD6402 has multiple power-down modes to maximize
battery life. It operates over a temperature range of –25°C to
+85°C and is packaged in a JEDEC standard 28-lead small-
shrink outline (SSOP) surface-mount package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997




AD6402 pdf, 반도체, 판매, 대치품
AD6402
VTUNE
1nF
1.2k
47pF
8pF
39nH
VCO
VCOGND
4.7nF
SMV
1204-37
SMV
1204-36
240
TXIF+
TXIF–
1nF TXOUT
1nF TXOUTB
330
150pF
VCCI
AD6402
MODOUT
FMMOD2
FMMOD1
330
100pF
330
180pF
TXMOD
Figure 1.
OVERVIEW
The AD6402 forms the basis of a highly integrated RF trans-
ceiver with the benefits of increased sensitivity and wide dy-
namic range that a dual-conversion architecture provides. The
IC contains a low dropout voltage regulator to isolate the IF and
demodulator VCOs from variation in the battery voltage, such
as power-supply transients caused by the PA. The AD6402 also
provides control circuitry that allows subcircuits to be turned off
and on as necessary to minimize power consumption.
Operation During Receive
The AD6402 contains the second mixer, integrated second-IF
bandpass filter, logarithmic-limiting amplifier, and PLL de-
modulator. A SAW IF bandpass filter is usually required at the
IF input in order to provide channel selectivity.
The placement of the SAW filter in the signal path between
the AD6402 and the RF section and the partitioning of the
receiver’s RF and IF receive circuits minimizes the leakage
around the SAW filter and maximizes the RF to IF isolation.
The output of the SAW filter enters the AD6402 via the second
downconversion mixer. This mixer is a high gain, doubly-
balanced Gilbert-cell type. The mixer downconverts the signal
to the second IF, which is 1.5 × or 2.5 × the reference frequency.
This multiple is determined by the state of the REFSEL pin. An
on-chip two section bandpass filter provides additional selectiv-
ity to provide attenuation of adjacent channels. The VCO con-
trol voltage output of the PLL demodulator tunes this filter to
the second IF.
The bandpass filter’s output enters a successive-detection loga-
rithmic-limiting IF amplifier. The RSSI detectors are distrib-
uted across the entire IF strip, including the mixer, and provide
80 dB RSSI range. The IF strip’s limiting gain also exceeds 80
dB. The RSSI signal is low-pass filtered and proceeds off-chip
to the baseband subsystem. The limited output of the logarith-
mic amplifier enters a PLL demodulator, which provides de-
modulation of the received signal. The PLL uses an integrated
VCO with no external components.
Operation During Transmit
The transmit signal path consists of a low-pass filter that can be
user configured for antialiasing of a baseband transmit signal.
An IF VCO, which should be tuned to a frequency equal to the
receive IF frequency plus the desired demodulator input fre-
quency, may be open-loop modulated by the transmit signal for
FM and FSK schemes. The receive IF mixer uses high side
mixing and therefore the IF VCO should be set to a frequency
equal to the sum of the IF frequency plus the frequency of the
PLL demodulator input as defined by the reference clock
divider ratios.
The transmit IF VCO uses an external tank circuit. This signal
is upconverted to the transmit frequency in the RF mixer sec-
tion of the radio. Using a transmit IF VCO prevents two prob-
lems: feedback from the PA at the RF frequency does not cause
distortion in the modulating circuit because the frequencies are
widely separated and the IF tank circuit can be optimized for
modulation linearity.
The output of the transmit VCO passes through buffer amplifier
and leaves the AD6402 via an optional LC filter between the RF
and IF ICs. The output of the LC filter may then be fed to a
transmit upconversion mixer for conversion to the final RF
frequency.
Onboard Voltage Regulation
The AD6402 contains a low dropout voltage regulator to spe-
cifically isolate the VCOs and synthesizer from the voltage
“kick” that occurs when a power amplifier switches on and the
battery voltage abruptly drops. The AD6402 uses an integral
vertical PNP pass transistor.
The regulator in the AD6402 IF IC supplies the voltage for the
VCOs on both the RF section and AD6402. The other sections
of the AD6402 should be powered from an independently regu-
lated source at 2.85 V. Since the VCOs are isolated from this
source, possible problems due to VCO supply pushing are con-
siderably reduced.
Frequency Control
The AD6402 requires an external synthesizer to provide the
control voltages for the tank circuit of the IF VCO. Normally
this will be the IF section of a dual synthesizer controlling both
IF and RF frequency generation.
It is recommended that the VCO on the RF section implement
the channel selection on transmit and receive; the VCO on the
AD6402 may therefore operate at a fixed frequency. This ac-
complishes two goals: first, the IF VCO being modulated can be
optimized for modulation linearity and the RF VCO can be
optimized for tuning range, and second, feedback from the PA
at will not couple into the modulating circuit to cause spurious
responses.
All key sections of the AD6402 may be powered up or down as
necessary to minimize power consumption and maximize
battery life.
–4– REV. 0

4페이지










AD6402 전자부품, 판매, 대치품
AD6402
IFIN
C69
1nF
L5
150nH
VTUNE
C25
1nF
1 10
29
38
47
5 B4535 6
VRF
C44
100nF
IFVCC1
AD6402
L7
100nH
L6
150nH
C10
1nF
12pF
IFIN
IFGND
VCC C44
1nF
R26 C42
1.2k47pF
C41
8pF
C50
4.7nF
D3 D2
SMV
1204-37
L11
39nH
SMV
1204-36
R21
240
VIF
C43
100nF
VREF
VBAT
VREG
REG
SLREF REF
VCO
VCOGND
IFC2
IFC1
IFC0
TXIF+
TXIF–
CTL3
CTL2
CTL1
C28
1nF
TXOUT
TXOUTB
C29
1nF
C30
150pF
R16
330
IFVCC2
C71
1nF
RSSI
DOUT
DFILP
R8
4.7k
C12
33pF
C4
3.3nF
RSSI
RXBB
R30 C58 R35
2k47pF 4.7k
PLLOUT
PLLVCC
PLLGND
REXT
R10 R9
2k1k
VRF
C11
100pF
R17
10k
C14
68pF
/3,/5
CFILT
CP
COFF
C45 R22
131nF 330
CP PD CP
C32
REFIN 100nF
REFSEL
C13
1nF
C31
R70
RCLK
FMMOD2
FMMOD1
C52
100pF
R28
330
R32
330
TXBB
MODOUT
C51
180pF
Figure 5. Application Circuit for DECT GFSK Transceiver
supply current levels when not allocated to an active transmit or
receive timeslot in a TDMA system.. The respective transmit
and receive blocks can be turned on only as needed thereby
reducing power consumption and extending battery life of
handheld terminals.
The component selection in Figure 5 is explained as follows:
The IF input is driven from the output of a SAW filter via an
impedance matching circuit as shown. This matching minimizes
the insertion loss of the filter and follows the filter manufactur-
ers recommendations. The tank circuit shown uses two varactor
diodes. One diode (D3) is biased by the output of the IF PLL
loop filter and ensures that the IF VCO frequency is correctly
centered. The second diode is provided to enable a modulation
signal, which is generated at the output of the on-chip op amp
(MODOUT), to be coupled into the VCO tank and thereby
implement a modulation of the VCO frequency. In the case of
DECT, the IF VCO control loop is opened while the VCO is
being modulated by the transmit bit stream. The loop is opened
by tri-stating the output of the IF VCO PLL charge pump.
The exact component values used around the modulation am-
plifier will be determined by the amount of attenuation required
for suppression of baseband transmit spurii and images. These
artifacts are usually present if the baseband FSK signal is gener-
ated by a ROMDAC. In most instances a second or third order
Bessel or Butterworth filter will be required.
A capacitor to ground is required to be connected to COFF.
This capacitor stores the demodulator charge-pump voltage
required to lock the demodulator VCO to the reference fre-
quency. The dynamic response of the demodulator loop is con-
trolled by selection of the values for C45 and R22 which are
connected in series to CFILT. These components determine the
transfer characteristic of the loop filter and hence the lock time,
settling time and bandwidth of the loop. REXT should use the
recommended value as shown.
Finally, the demodulator is followed by a voltage follower,
which is configured as a data filter. This data filter is used to
bandlimit the FM noise generated in the demodulator. It also
attenuates undesired adjacent channel interferers. The compo-
nent values chosen will be a trade-off between the amount of
band limiting required and attenuation of the in-band desired
signal.
DECT Application Circuit Notes (Figure 5)
1. Signal Description
VRF: Regulated Supply Voltage; Nominal Value 2.85 V.
VCC: Unregulated battery voltage; 3.1 V–4.5 V
VTUNE: Synthesizer Control Voltage; Range dependent on
loop filter and synth charge pump compliance.
TXBB: Baseband transmit modulation voltage; typically
SLREF ± 0.7 V
RCLK: Reference clock for PLL demodulator; 13.824 MHz
(2nd IF frequency = (N/M) × Frclk where N = 3 or 5, and
M = 2. Maximum 2nd IF = c.26 MHz)
2. Typical IF input sensitivity referred to the input of SAW
filter for the above application will be –72 dBm.
3. TxBB filter is user configurable. In the above application, the
filter is implemented to remove images generated by ROM
DAC baseband signal generators. Other implementations are
possible including passive pulse shaping circuits which elimi-
nate the need for such filtering.
REV. 0
–7–

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