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부품번호 AD641 기능
기능 250 MHz Demodulating Logarithmic Amplifier
제조업체 Analog Devices
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AD641 데이터시트, 핀배열, 회로
a
250 MHz Demodulating
Logarithmic Amplifier
AD641
FEATURES
Logarithmic Amplifier Performance
Usable to 250 MHz
44 dB Dynamic Range
؎2.0 dB Log Conformance
37.5 mV/dB Voltage Output
Stable Slope and Intercepts
2.0 nV/Hz Input Noise Voltage
50 V Input Offset Voltage
Low Power
؎5 V Supply Operation
9 mA (+VS), 35 mA (–VS) Quiescent Current
Onboard Resistors
Onboard 10؋ Attenuator
Dual Polarity Current Outputs
Direct Coupled Differential Signal Path
APPLICATIONS
IF/RF Signal Processing
Received Signal Strength Indicator (RSSI)
High Speed Signal Compression
High Speed Spectrum Analyzer
ECM/Radar
PRODUCT DESCRIPTION
The AD641 is a 250 MHz, demodulating logarithmic amplifier
with an accuracy of ± 2.0 dB and 44 dB dynamic range. The
AD641 uses a successive detection architecture to provide an
output current that is logarithmically proportional to its input
voltage. The output current can be converted to a voltage using
one of several on-chip resistors to select the slope. A single
AD641 provides up to 44 dB of dynamic range at speeds up to
250 MHz, and two cascaded AD641s together can provide
58 dB of dynamic range at speeds up to 250 MHz. The AD641
is fully stable and well characterized over either the industrial or
military temperature ranges.
The AD641 is not a logarithmic building block, but rather a
complete logarithmic solution for compressing and measuring
wide dynamic range signals. The AD641 is comprised of five
stages and each stage has a full wave rectifier, whose current
depends on the absolute value of its input voltage. The output
of these stages are summed together to provide the demodulated
output current scaled at 1 mA per decade (50 µA/dB).
Without utilizing the 10× input attenuator, log conformance of
2.0 dB is maintained over the input range –44 dBm to 0 dBm.
The attenuator offers the most flexibility without significantly
impacting performance.
PIN CONFIGURATIONS
20-Lead Plastic DIP (N)
20-Lead Cerdip (Q)
–INPUT 1
20 +INPUT
ATN LO 2
19 ATN OUT
ATN COM 3
18 CKT COM
ATN COM 4
17 RG1
ATN IN
BL1
–VS
5 AD641 16 RG0
6 TOP VIEW 15 RG2
(Not to Scale)
7 14 LOG OUT
ITC 8
13 LOG COM
BL2 9
–OUTPUT 10
12 +VS
11 +OUTPUT
20-Lead PLCC (P)
ATN COM 4
ATN IN 5
BL1 6
–VS 7
ITC 8
3 2 1 20 19
PIN 1
18 CKT COM
IDENTIFIER
AD641
TOP VIEW
17 RG1
16 RG0
(Not to Scale)
15 RG2
14 LOG OUT
9 10 11 12 13
The 250 MHz bandwidth and temperature stability make this
product ideal for high speed signal power measurement in RF/
IF systems. ECM/Radar and Communication applications are
routinely in the 100 MHz–180 MHz range for power measure-
ment. The bandwidth and accuracy, as well as dynamic range,
make this part ideal for high speed, wide dynamic range signals.
The AD641 is offered in industrial (–40°C to +85°C) and mili-
tary (–55°C to +125°C) package temperature ranges. Industrial
versions are available in plastic DIP and PLCC; MIL versions
are packaged in cerdip.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999




AD641 pdf, 반도체, 판매, 대치품
AD641–Typical DC Performance Characteristics
1.015
1.010
1.005
1
0.995
0.990
0.985
0.980
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – ؇C
Figure 1. Slope Current, IY, vs.
Temperature
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – ؇C
Figure 2. Intercept Voltage, VX, vs.
Temperature
1.006
1.004
1.002
1.000
0.998
0.996
0.994
4.5 5.0 5.5 6.0 6.5 7.0 7.5
POWER SUPPLY VOLTAGES – ؎ Volts
Figure 3. Slope Current, IY, vs. Supply
Voltages
1.015
1.010
1.005
1.000
0.995
0.990
0.985
4.5 5.0 5.5 6.0 6.5 7.0 7.5
POWER SUPPLY VOLTAGES – ؎ Volts
Figure 4. Intercept Voltage, VX, vs.
Supply Voltages
14
13
12
11
10
9
8
7
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – ؇C
Figure 5. Intercept Voltage (Using
Attenuator) vs. Temperature
+0.4
+0.3
+0.2
+0.1
INPUT OFFSET VOLTAGE
DEVIATION WILL BE WITHIN
SHADED AREA.
0
–0.1
–0.2
–0.3
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – ؇C
Figure 6. Input Offset Voltage Devia-
tion vs. Temperature
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
0.1
2
1
0
1.0
10.0
100.0
INPUT VOLTAGE – mV
(EITHER SIGN)
1000.0
Figure 7. DC Logarithmic Transfer
Function and Error Curve for Single
AD641
2.5 2.5
2.0 2.0
1.5 1.5
1.0 1.0
0.5 0.5
0
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – ؇C
Figure 8. Absolute Error vs. Tempera-
ture, VIN = ±1 mV to ±100 mV
0
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – ؇C
Figure 9. Absolute Error vs. Tempera-
ture, Using Attenuator. VIN = ±10 mV
to ±1 V, Pin 8 Grounded to Disable ITC
Bias
–4– REV. C

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AD641 전자부품, 판매, 대치품
AD641
Transistors Q3 through Q6 form the full wave detector, whose
output is buffered by the cascodes Q9 and Q10. For zero input
Q3 and Q5 conduct only a small amount (a total of about 32 µA)
of the 565 µA tail currents supplied to pairs Q3–Q4 and Q5–Q6.
This “pedestal” current flows in output cascode Q9 to the LOG
OUT node (Pin 14). When driven to the peak output of the
preceding stage, Q3 or Q5 (depending on signal polarity) con-
ducts most of the tail current, and the output rises to 532 µA.
The LOG OUT current has thus changed by 500 µA as the
input has changed from zero to its maximum value. Since the
detectors are spaced at 10 dB intervals, the output increases by
50 µA/dB, or 1 mA per decade. This scaling parameter is trimmed
to absolute accuracy using a 2 kHz square wave. At frequencies
near the system bandwidth, the slope is reduced due to the
reduced output of the limiter stages, but it is still relatively in-
sensitive to temperature variations so that a simple external
slope adjustment can restore scaling accuracy.
The intercept position bias generator (Figure 17) removes the
pedestal current from the summed detector outputs. It is ad-
justed during manufacture such that the output (flowing into
Pin 14) is 1 mA when a 2 kHz square-wave input of exactly
± 10 mV is applied to the AD641. This places the dc intercept at
precisely 1 mV. The LOG COM output (Pin 13) is the comple-
ment of LOG OUT. It also has a 1 mV intercept, but with an
inverted slope of –1 mA/decade. Because its pedestal is very
large (equivalent to about 100 dB), its intercept voltage is not
guaranteed. The intercept positioning currents include a special
internal temperature compensation (ITC) term which can be
disabled by connecting Pin 8 to ground.
The logarithmic function of the AD641 is absolutely calibrated
to within ± 0.3 dB (or ± 15 µA) for 2 kHz square-wave inputs of
± 1 mV to ± 100 mV, and to within ±1 dB between ± 750 µV and
±200 mV. Figure 18 is a typical plot of the dc transfer function,
2.5
3
+125؇C 2
2.0
+25؇C
–55؇C
1
0
1.5
–55؇C
–1
+25؇C +125؇C
–2
1.0
0.5
0
–0.5
0.1
1.0
10.0
100.0
INPUT VOLTAGE – mV
1000.0
Figure 18. Logarithmic Output and Absolute Error vs. DC
or Square Wave Input at TA = –55°C, +25°C, and +125°C,
Input Direct to Pins 1 and 20
2.5
+25؇C
–55؇C
2.0
+85؇C +125؇C
1.5
1
0
–1
–2
1.0
0.5
0
–0.5
0.1
10 100 1000
INPUT VOLTAGE – mV
10000
Figure 19. Logarithmic Output and Absolute Error vs. DC
or Square Wave Input at TA = –55°C, +25°C, +85°C and
+125°C. Input via On-Chip Attenuator
showing the outputs at temperatures of –55°C, +25°C and
+125°C. While the slope and intercept are seen to be little af-
fected by temperature, there is a lateral shift in the end points of
the “linear” region of the transfer function, which reduces the
effective dynamic range.
The on chip attenuator can be used to handle input levels 20 dB
higher, that is, from ± 7.5 mV to ± 2 V for dc or square wave
inputs. It is specially designed to have a positive temperature
coefficient and is trimmed to position the intercept at 10 mV dc
(or –24 dBm for a sinusoidal input) over the full temperature
range. When using the attenuator the internal bias compensa-
tion should be disabled by grounding Pin 8. Figure 19 shows
the output at –55°C, +25°C, +85°C and +125°C for a single,
AD641 with the attenuator in use; the curves overlap almost
perfectly, and the lateral shift in the transfer function does not
occur. Therefore, the full dynamic range is available at all
temperatures.
The output of the final limiter is available in differential form at
Pins 10 and 11. The output impedance is 75 to ground from
either pin. For most input levels, this output will appear to have
roughly a square waveform. The signal path may be extended
using these outputs (see OPERATION OF CASCADED
AD641s). The logarithmic outputs from two or more AD641s
can be directly summed with full accuracy.
A pair of 1 kapplications resistors, RG1 and RG2 (Figure 17)
are accessed via Pins 15, 16 and 17. These can be used to con-
vert an output current to a voltage, with a slope of 1 V/decade
(using one resistor), 2 V/decade (both resistors in series) or
0.5 V/decade (both in parallel). Using all the resistors from two
AD641s (for example, in a cascaded configuration) ten slope
options from 0.25 V to 4 V/decade are available.
REV. C
–7–

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