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AD650 데이터시트 PDF




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부품번호 AD650 기능
기능 Voltage-to-Frequency and Frequency-to-Voltage Converter
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AD650 데이터시트, 핀배열, 회로
a
FEATURES
V/F Conversion to 1 MHz
Reliable Monolithic Construction
Very Low Nonlinearity
0.002% typ at 10 kHz
0.005% typ at 100 kHz
0.07% typ at 1 MHz
Input Offset Trimmable to Zero
CMOS or TTL Compatible
Unipolar, Bipolar, or Differential V/F
V/F or F/V Conversion
Available in Surface Mount
MIL-STD-883 Compliant Versions Available
Voltage-to-Frequency and
Frequency-to-Voltage Converter
AD650
PIN CONFIGURATION
PRODUCT DESCRIPTION
The AD650 V/F/V (voltage-to-frequency or frequency-to-voltage
converter) provides a combination of high frequency operation
and low nonlinearity previously unavailable in monolithic form.
The inherent monotonicity of the V/F transfer function makes
the AD650 useful as a high-resolution analog-to-digital converter.
A flexible input configuration allows a wide variety of input volt-
age and current formats to be used, and an open-collector output
with separate digital ground allows simple interfacing to either
standard logic families or opto-couplers.
The linearity error of the AD650 is typically 20 ppm (0.002%
of full scale) and 50 ppm (0.005%) maximum at 10 kHz full
scale. This corresponds to approximately 14-bit linearity in an
analog-to-digital converter circuit. Higher full-scale frequencies
or longer count intervals can be used for higher resolution con-
versions. The AD650 has a useful dynamic range of six decades
allowing extremely high resolution measurements. Even at 1 MHz
full scale, linearity is guaranteed less than 1000 ppm (0.1%) on
the AD650KN, BD, and SD grades.
In addition to analog-to-digital conversion, the AD650 can be used
in isolated analog signal transmission applications, phased locked-
loop circuits, and precision stepper motor speed controllers. In
the F/V mode, the AD650 can be used in precision tachometer
and FM demodulator circuits.
The input signal range and full-scale output frequency are user-
programmable with two external capacitors and one resistor.
Input offset voltage can be trimmed to zero with an external
potentiometer.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
The AD650JN and AD650KN are offered in a plastic 14-lead
DIP package. The AD650JP is available in a 20-lead plastic
leaded chip carrier (PLCC). Both plastic packaged versions of the
AD650 are specified for the commercial (0°C to +70°C) tempera-
ture range. For industrial temperature range (–25°C to +85°C)
applications, the AD650AD and AD650BD are offered in a
ceramic package. The AD650SD is specified for the full –55°C
to +125°C extended temperature range.
PRODUCT HIGHLIGHTS
1. In addition to very high linearity, the AD650 can operate at
full-scale output frequency up to 1 MHz. The combination of
these two features makes the AD650 an inexpensive solution
for applications requiring high resolution monotonic A/D
conversion.
2. The AD650 has a very versatile architecture that can be con-
figured to accommodate bipolar, unipolar, or differential
input voltages, or unipolar input currents.
3. TTL or CMOS compatibility is achieved using an open
collector frequency output. The pull-up resistor can be
connected to voltages up to +30 V, or +15 V or +5 V for
conventional CMOS or TTL logic levels.
4. The same components used for V/F conversion can also be
used for F/V conversion by adding a simple logic biasing net-
work and reconfiguring the AD650.
5. The AD650 provides separate analog and digital grounds.
This feature allows prevention of ground loops in real-world
applications.
6. The AD650 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD650/883B data sheet for detailed
specifications.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000




AD650 pdf, 반도체, 판매, 대치품
AD650
CIRCUIT OPERATION
UNIPOLAR CONFIGURATION
The AD650 is a charge balance voltage-to-frequency converter. In
the connection diagram shown in Figure 1, or the block diagram
of Figure 2a, the input signal is converted into an equivalent cur-
rent by the input resistance RIN. This current is exactly balanced
by an internal feedback current delivered in short, timed bursts
from the switched 1 mA internal current source. These bursts of
current may be thought of as precisely defined packets of charge.
The required number of charge packets, each producing one
pulse of the output transistor, depends upon the amplitude of
the input signal. Since the number of charge packets delivered
per unit time is dependent on the input signal amplitude, a linear
voltage-to-frequency transformation will be accomplished. The
frequency output is furnished via an open collector transistor.
A more rigorous analysis demonstrates how the charge balance
voltage-to-frequency conversion takes place.
A block diagram of the device arranged as a V-to-F converter is
shown in Figure 2a. The unit is comprised of an input integra-
tor, a current source and steering switch, a comparator and a
one-shot. When the output of the one-shot is low, the current
steering switch S1 diverts all the current to the output of the op
amp; this is called the Integration Period. When the one-shot
has been triggered and its output is high, the switch S1 diverts
all the current to the summing junction of the op amp; this is
called the Reset Period. The two different states are shown in
Figure 2 along with the various branch currents. It should be
noted that the output current from the op amp is the same for
either state, thus minimizing transients.
Figure 1. Connection Diagram for V/F Conversion,
Positive Input Voltage
Figure 2a. Block Diagram
Figure 2b. Reset Mode
Figure 2c. Integrate Mode
Figure 2d. Voltage Across CINT
The positive input voltage develops a current (IIN = VIN/RIN)
which charges the integrator capacitor CINT. As charge builds up
on CINT, the output voltage of the integrator ramps downward
towards ground. When the integrator output voltage (Pin 1)
crosses the comparator threshold (–0.6 volt) the comparator
triggers the one shot, whose time period, tOS is determined by
the one shot capacitor COS.
Specifically, the one shot time period is:
tOS = COS × 6.8 × 103 sec /F + 3.0 × 10–7 sec
(1)
The Reset Period is initiated as soon as the integrator output
voltage crosses the comparator threshold, and the integrator
ramps upward by an amount:
( )dV
V = tOS dt
= tOS
CINT
1mA IN
(2)
After the Reset Period has ended, the device starts another Inte-
gration Period, as shown in Figure 2, and starts ramping downward
again. The amount of time required to reach the comparator
threshold is given as:
TI =
V
dV
dt
=
tOS/CINT(1 mA IIN )
IN /CINT
=
tOS
1 mA
IIN
– 1
The output frequency is now given as:
(3)
fOUT
=
1
tOS + TI
=
IIN
tOS × 1 mA
= 0.15
F Hz
A
VIN /RIN
COS + 4.4 × 10–11F
(4)
Note that CINT, the integration capacitor has no effect on the
transfer relation, but merely determines the amplitude of the
sawtooth signal out of the integrator.
One Shot Timing
A key part of the preceding analysis is the one shot time period
that was given in equation (1). This time period can be broken
down into approximately 300 ns of propagation delay, and a sec-
ond time segment dependent linearly on timing capacitor COS.
When the one shot is triggered, a voltage switch that holds Pin 6
–4– REV. C

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AD650 전자부품, 판매, 대치품
AD650
Figure 7. 1 MHz V/F Connection Diagram
DECOUPLING AND GROUNDING
It is good engineering practice to use bypass capacitors on the
supply-voltage pins and to insert small-valued resistors (10 to
100 ) in the supply lines to provide a measure of decoupling
between the various circuits in a system. Ceramic capacitors of
0.1 µF to 1.0 µF should be applied between the supply-voltage
pins and analog signal ground for proper bypassing on the AD650.
In addition, a larger board level decoupling capacitor of 1 µF to
10 µF should be located relatively close to the AD650 on each
power supply line. Such precautions are imperative in high reso-
lution data acquisition applications where one expects to exploit
the full linearity and dynamic range of the AD650. Although
some types of circuits may operate satisfactorily with power sup-
ply decoupling at only one location on each circuit board, such
practice is strongly discouraged in high accuracy analog design.
Separate digital and analog grounds are provided on the AD650.
The emitter of the open collector frequency output transistor is
the only node returned to the digital ground. All other signals
are referred to analog ground. The purpose of the two separate
grounds is to allow isolation between the high precision analog
signals and the digital section of the circuitry. As much as sev-
eral hundred millivolts of noise can be tolerated on the digital
ground without affecting the accuracy of the VFC. Such ground
noise is inevitable when switching the large currents associated
with the frequency output signal.
At 1 MHz full scale, it is necessary to use a pull-up resistor of
about 500 in order to get the rise time fast enough to provide
well defined output pulses. This means that from a 5 volt logic
supply, for example, the open collector output will draw 10 mA.
This much current being switched will surely cause ringing on
long ground runs due to the self inductance of the wires. For
instance, #20 gauge wire has an inductance of about 20 nH per
inch; a current of 10 mA being switched in 50 ns at the end of
12 inches of 20 gauge wire will produce a voltage spike of 50 mV.
The separate digital ground of the AD650 will easily handle
these types of switching transients.
A problem will remain from interference caused by radiation of
electro-magnetic energy from these fast transients. Typically, a
voltage spike is produced by inductive switching transients;
these spikes can capacitively couple into other sections of the
circuit. Another problem is ringing of ground lines and power
supply lines due to the distributed capacitance and inductance
of the wires. Such ringing can also couple interference into sen-
sitive analog circuits. The best solution to these problems is
proper bypassing of the logic supply at the AD650 package. A
1 µF to 10 µF tantalum capacitor should be connected directly
to the supply side of the pull-up resistor and to the digital
ground—Pin 10. The pull-up resistor should be connected
directly to the frequency output—Pin 8. The lead lengths on the
bypass capacitor and the pull up resistor should be as short as
possible. The capacitor will supply (or absorb) the current tran-
sients, and large ac signals will flow in a physically small loop
through the capacitor, pull up resistor, and frequency output
transistor. It is important that the loop be physically small for
two reasons: first, there is less self-inductance if the wires are
short, and second, the loop will not radiate RFI efficiently.
The digital ground (Pin 10) should be separately connected to
the power supply ground. Note that the leads to the digital
power supply are only carrying dc current and cannot radiate
RFI. There may also be a dc ground drop due to the difference
in currents returned on the analog and digital grounds. This will
not cause any problem. In fact, the AD650 will tolerate as much
as 0.25 volt dc potential difference between the analog and digital
grounds. These features greatly ease power distribution and
ground management in large systems. Proper technique for
grounding requires separate digital and analog ground returns to
the power supply. Also, the signal ground must be referred
directly to analog ground (Pin 11) at the package. All of the sig-
nal grounds should be tied directly to Pin 11, especially the
one-shot capacitor. More information on proper grounding and
reduction of interference can be found in Reference 1.
TEMPERATURE COEFFICIENTS
The drift specifications of the AD650 do not include temperature
effects of any of the supporting resistors or capacitors. The drift
of the input resistors R1 and R3 and the timing capacitor COS
directly affect the overall temperature stability. In the application
of Figure 2, a 10 ppm/°C input resistor used with a 100 ppm/°C
capacitor may result in a maximum overall circuit gain drift of:
150 ppm/°C (AD650A) + 100 ppm/°C (COS) + 10 ppm/°C (RIN) 260 ppm/°C
In bipolar configuration, the drift of the 1.24 kresistor used to
activate the internal bipolar offset current source will directly
affect the value of this current. This resistor should be matched
to the resistor connected to the op amp noninverting input (Pin
2), see Figure 4. That is, the temperature coefficients of these
two resistors should be equal. If this is the case, then the effects
of the temperature coefficients of the resistors cancel each other,
and the drift of the offset voltage developed at the op amp non-
inverting input will be determined solely by the AD650. Under
these conditions the TC of the bipolar offset voltage is typically
–200 ppm/°C and is a maximum of –300 ppm/°C. The offset
voltage always decreases in magnitude as temperature is increased.
Other circuit components do not directly influence the accuracy
of the VFC over temperature changes as long as their actual val-
ues are not so different from the nominal value as to preclude
operation. This includes the integration capacitor, CINT. A
change in the capacitance value of CINT simply results in a dif-
ferent rate of voltage change across the capacitor. During the
Integration Phase (refer to Figure 2), the rate of voltage change
across CINT has the opposite effect that it does during the Reset
Phase. The result is that the conversion accuracy is unchanged
1“Noise Reduction Techniques in Electronic Systems,” by H. W. OTT,
(John Wiley, 1976).
REV. C
–7–

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