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AD6600 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD6600은 전자 산업 및 응용 분야에서
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부품번호 AD6600 기능
기능 Dual Channel/ Gain-Ranging ADC with RSSI
제조업체 Analog Devices
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AD6600 데이터시트, 핀배열, 회로
a
Dual Channel, Gain-Ranging
ADC with RSSI
AD6600
FEATURES
Dual IF Inputs, 70 MHz–250 MHz
Diversity or Two Independent IF Signals
Separate Attenuation Paths
Oversample RF Channels
20 MSPS on a Single Carrier
10 MSPS/Channel in Diversity Mode
Total Signal Range 90+ dB
30 dB from Automatic Gain-Ranging (AGC)
60 dB from A/D Converter
Range >100 dB After Processing Gain
Digital Outputs
11-Bit ADC Word
3-Bit RSSI Word
2؋ Clock, A/B Indicator
Single 5 V Power Supply
Output DVCC 3.3 V or 5 V
775 mW Power Dissipation
APPLICATIONS
Communications Receivers
PCS/Cellular Base Stations
GSM, CDMA, TDMA
Wireless Local Loop, Fixed Access
PRODUCT DESCRIPTION
The AD6600 mixed-signal receiver chip directly samples signals
at analog input frequencies up to 250 MHz. The device includes
two input channels, each with 1 GHz input amplifiers and
30 dB of automatic gain-ranging circuitry. Both channels are
sampled with a 450 MHz track-and-hold followed by an 11-bit,
20 MSPS analog-to-digital converter. Digital RSSI outputs, an
A/B channel indicator, a 2× Clock output, references, and con-
trol circuitry are all on-chip. Digital output signals are two’s
complement, CMOS-compatible and interface directly to
3.3 V or 5 V digital processing chips.
The primary use for the dual analog input structure is sampling
both antennas in a two-antenna diversity receiver. However,
Channels A and B may also be used to sample two independent
IF signals. Diversity, or dual-channel mode, is limited to 10 MSPS
per channel. In single-channel mode, the full clock rate of
20 MSPS may be applied to a single carrier.
The AD6600 may be used as a stand-alone sampling chip, or it
may be combined with the AD6620 Digital Receive Signal Pro-
cessor. The AD6620 provides 10 dB–25 dB of additional pro-
cessing gain before passing data to a fixed- or floating-point DSP.
Driving the AD6600 is simplified by using the AD6630 differen-
tial IF amplifier. The AD6630 is easily matched to inexpensive
SAW filters from 70 MHz to 250 MHz.
Designed specifically for cellular/PCS receivers, the AD6600
supports GSM, IS-136, CDMA and Wireless LANs, as well as
proprietary air interfaces used in WLL/fixed-access systems.
Units are available in plastic, surface-mount packages (44-lead
LQFP) and specified over the industrial temperature range
(–40°C to +85°C).
FUNCTIONAL BLOCK DIAGRAM
NOISE FILTER
0dB, –12dB, –24dB
AIN
ATTEN
AIN
DETECT SET
PEAK RSSI
GAIN
3
RSSI
GAIN
BIN
ATTEN
BIN
0dB, –12dB, –24dB
FLT FLT
630
RESONANT
PORT
+12, +18dB
GAIN
SELECT GAIN
ENCODE
TWO'S
A/D COMPLEMENT
CONVERTER
11
ENCODE
3
RSSI
AB_OUT
D10–D0
RSSI [2:0]
AD6600
TIMING
CLK2؋
REV. 0
A_SEL B_SEL
AVCC GND
ENC ENC
DVCC
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000




AD6600 pdf, 반도체, 판매, 대치품
AD6600–SPECIFICATIONS
TIMING REQUIREMENTS AND SWITCHING SPECIFICATIONS1, 2
(AVCC = 5 V, DVCC = 3.3 V; ENC and ENC = 20 MSPS, Duty Cycle = 50%; TMIN = –40؇C, TMAX = +85؇C unless otherwise noted.)
Parameter
Name
Temp
Test
Level
AD6600AST
Min Typ
Max
Unit
ENCODE/CLK2×
Encode Rising to CLK2× Falling3
Encode Rising to CLK2× Rising4
@ Encode = 13 MSPS, 50% Duty Cycle
@ Encode = 20 MSPS, 50% Duty Cycle
tCF
tCR
Full IV
Full IV
Full IV
Full IV
6.5 8.0
9.5 ns
25.7
tCF + (tENCH)/2
27.2
28.7
ns
ns
19.0 20.5
22.0 ns
CLK2×/DATA (D10:0, RSSI2:0)5
CLK2× to DATA Rising Low Delay3
CLK2× to DATA Hold Time3
CLK2× to DATA Falling Low3, 6
CLK2× to DATA Setup Time4
@ Encode = 13 MSPS, 50% Duty Cycle
@ Encode = 20 MSPS, 50% Duty Cycle6
t2×_DRL
tH_D2×
t2×_DFL
tS_D2×
Full
Full
25°C
Full
Full
Full
25°C
Full
IV
IV
IV
IV
IV
IV
IV
IV
3.0 6.5
ns
3.0 6.5
ns
10.0 15.0
20.0 ns
11.0 15.5
22.0 ns
16.5
tENCH – t2×_DFL
23.0
ns
ns
5.0 10.0
ns
3.0 9.5
ns
CLK2×/AB_OUT5
CLK2× to AB_OUT Rising Low Delay3
CLK2× to AB_OUT Hold Time3
CLK2× to AB_OUT Falling Low Delay3, 6
CLK2× to AB_OUT Setup Time4
@ Encode = 13 MSPS, 50% Duty Cycle
@ Encode = 20 MSPS, 50% Duty Cycle6
t2×_ARL
tH_A2×
t2×_AFL
tS_A2×
Full
Full
25°C
Full
Full
Full
25°C
Full
IV
IV
IV
IV
IV
IV
IV
IV
7.0 11.0
ns
7.0 11.0
ns
12.0 18.0
23.0 ns
10.7 19.0
26.0 ns
12.5
tENCH – t2×_AFL
19.5
ns
ns
2.0 7.0
ns
–1.0 6.0
ns
ENCODE/DATA (D10:0, RSSI2:0)
ENCODE to DATA Rising Low Delay4
ENCODE to DATA Hold Time4
@ Encode = 13 MSPS, 50% Duty Cycle
@ Encode = 20 MSPS, 50% Duty Cycle
ENCODE to DATA Falling Low Delay4
ENCODE to DATA Delay (Setup)4
@ Encode = 13 MSPS, 50% Duty Cycle
@ Encode = 20 MSPS, 50% Duty Cycle6
tEN_DRL
tH_DEN
tEN_DFL
tS_DEN
Full
Full
Full
Full
Full
Full
Full
25°C
Full
IV
IV
IV
IV
IV
IV
IV
IV
IV
28.7
22.0
26.2
8.0
6.0
tCR + t2×_DRL
tEN_DRL
33.7
27.0
tCR + t2×_DFL
tENC – tEN_DFL
34.2
14.5
14.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ENCODE/AB_OUT
ENCODE to AB_OUT Rising Low Delay4
ENCODE to AB_OUT Delay (Hold)4
@ Encode = 13 MSPS, 50% Duty Cycle
@ Encode = 20 MSPS, 50% Duty Cycle
ENCODE to AB_OUT Falling Low Delay4
ENCODE to AB_OUT Delay (Setup)4
@ Encode = 13 MSPS, 50% Duty Cycle
@ Encode = 20 MSPS, 50% Duty Cycle6
tEN_ARL
tH_AEN
tEN_AFL
tS_AEN
Full
Full
Full
Full
Full
Full
Full
25°C
Full
IV
IV
IV
IV
IV
IV
IV
IV
IV
32.7
26.0
22.2
5.0
2.0
tCR + t2×_ARL
tEN_ARL
38.2
31.5
tCR + t2×_AFL
tENC – tEN_AFL
30.7
11.5
10.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1See AD6600 Timing Diagrams.
2All switching specifications tested by driving ENC and ENC differentially.
3This specification IS NOT a function of Encode period and duty cycle.
4This specification IS a function of Encode period and duty cycle.
5CLK2× referenced to 2.0 V crossing; digital output levels referenced to 0.8 V and 2.0 V crossings; all outputs with 10 pF load.
6For these particular specifications, the 25°C specification is valid from 25°C to 85°C. The Full temperature specification includes cold temperature extreme and
covers the entire range, –40°C to +85°C.
Specifications subject to change without notice.
–4– REV. 0

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AD6600 전자부품, 판매, 대치품
AC SPECIFICATIONS (continued)
AD6600
Parameter
Temp
Test
Level
AD6600AST
Min Typ
Max
Unit
WORST OTHER SPUR (4th or Higher)
AIN = 70 MHz
@ –1 dBFS
@ –6 dBFS
@ –12 dBFS to –42 dBFS
AIN = 150 MHz
@ –1 dBFS
@ –6 dBFS
@ –12 dBFS to –42 dBFS
AIN = 200 MHz
@ –1 dBFS
@ –6 dBFS
@ –10 dBFS
@ –12 dBFS to –42 dBFS
AIN = 250 MHz
@ –1 dBFS
@ –6 dBFS
@ –12 dBFS to –42 dBFS
Full
Full
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
Full
Full
V
V
V
V
V
V
I
V
I
V
V
V
V
74.5
71
68 ± 6
67
65
67 ± 6
60 67
66
55 66
65 ± 6
66.5
65
65 ± 6
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
NOTES
1AIN, AIN/BIN, BIN: The AD6600 analog inputs are unconditionally stable and guarantee proper operation over the 70 MHz–250 MHz specified operating range.
Circuit board layout is critical on this device, and proper PCB layout must be employed to achieve specified results.
2Analog Input 3 dB Bandwidth is determined by internal track-and-hold. The front-end attenuators have a bandwidth of 1 GHz.
3Measured real and imaginary values using Network Analyzer.
4Full-scale gain tolerance is the typical variation in gain at a given IF input frequency. The nominal value for full-scale input power is a function of frequency as
shown in previous specification.
5Full-scale gain tolerance measured at 200 MHz analog input referenced to 6.7 dBm nominal full-scale input power. For the gain measurement test, the input signal
level is set to –6 dBFS. Tuning port bandwidth is set to 50 MHz.
6Main channel set to full-scale input power. Diversity channel swept from –20 dBFS to –90 dBFS.
7Measurement includes thermal and quantization noise at 70 MHz analog input. Tuning port bandwidth is set to 50 MHz.
8Test tones at 160.05 MHz and 170.05 MHz.
9Measurements at –1 dFBS, –6 dBFS, and –10 dBFS are in highest attenuation mode, RSSI = 101.
10Each gain-range is checked at ~3 dB from RSSI trip point (not in hysteresis); nominally –16 dBFS (RSSI = 100), –22 dBFS (RSSI = 011), –28 dBFS (RSSI = 010),
–35 dBFS (RSSI = 001).
11Measurement at –54 dBFS is in the lowest attenuation mode, RSSI = 000.
Specifications subject to change without notice.
REV. 0
–7–

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