AD6622 Datasheet PDF - Analog Devices
| Part Number | AD6622 | |
| Description | Four-Channel/ 75 MSPS Digital Transmit Signal Processor TSP | |
| Manufacturers | Analog Devices | |
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There is a preview and AD6622 download ( pdf file ) link at the bottom of this page. Total 28 Pages | ||
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FEATURES
Wideband Digital IF Parallel Output
Wideband Digital IF Parallel Input
Allows Cascade of Chips for Additional Channels
Programmable IF and Modulation for Each Channel
Programmable Interpolating RAM Coefficient Filter
High-Speed CIC Interpolating Filter
NCO Frequency Translation
Worst Spur Better than 100 dBc
Tuning Resolution Better than 0.02 Hz
Real or Complex Outputs
Digital Summation of Channels
Clipped or Wrapped Overrange
Two’s Complement or Offset Binary Output
Separate 3-Wire Serial Data Input for Each Channel
Microprocessor Control
JTAG Boundary Scan
APPLICATIONS
Cellular/PCS Base Stations
Micro/Pico Cell Base Stations
WBCDMA
Wireless Local Loop Base Stations
Phase Array Beam Forming Antennas
Four-Channel, 75 MSPS Digital
Transmit Signal Processor (TSP)
AD6622
FUNCTIONAL BLOCK DIAGRAM
CH A SPORT
RCF
CH B SPORT
RCF
CH C SPORT
RCF
CH D SPORT
RCF
JTAG
CIC
FILTER
CIC
FILTER
CIC
FILTER
CIC
FILTER
NCO
NCO
NCO
NCO
PORT
18
18
PRODUCT DESCRIPTION
The AD6622 comprises four identical digital Transmit Signal
Processors (TSPs) complete with synchronization circuitry and
cascadable wideband channel summation. An external digital-
to-analog converter (DAC) is all that is required to complete a
wide band digital up-converter. On-chip tuners allow the relative
phase and frequency for each RF carrier to be independently
controlled.
Each TSP has three cascaded signal processing elements: a
RAM-programmable Coefficient interpolating Filter (RCF), a
programmable Cascaded Integrator Comb (CIC) interpolating
filter, and a Numerically Controlled Oscillator/tuner (NCO).
The outputs of the four TSPs are summed and scaled on-chip.
In multichannel wideband transmitters, multiple AD6622s may
be combined using the chip’s cascadable output summation stage.
Each channel provides independent serial data inputs that may
be directly connected to the serial port of DSP chips. User pro-
grammable FIR filters can be used to filter linear inputs.
All control registers and coefficient values are programmed through
a generic microprocessor interface. Two microprocessor bus
modes are supported. All inputs and outputs are LVCMOS
compatible. All outputs are LVCMOS and 5 V TTL compatible.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
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RD (DS)
WR (R/W)
tHWR
AD6622
CS
A[2:0]
D[7:0]
RDY
(DTACK)
tSAM
VALID ADDRESS
tSAM
VALID DATA
tDRDY
tACC
tHAM
tHAM
1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM THE FE OF WR TO THE RE OF RDY.
2. tACCFAST REQUIRES A MAXIMUM OF THREE CLK PERIODS AND APPLIES TO A[2:0] = 7, 6, 5, 3, 2, 1
3. tACCMEDIUM REQUIRES A MAXIMUM OF FOUR CLK PERIODS AND APPLIES TO A[2:0] = 4 AND 0 IF THE ACCESS IS TO A CONTROL REGISTER
VERSUS A RAM REGISTER.
4. tACCSLOW REQUIRES A MAXIMUM OF FIVE CLK PERIODS AND APPLIES TO A[2:0] = 0 WHEN ACCESSING RAM REGISTERS.
Figure 5. INM Microport Write Timing Requirements
RD (DS)
WR (R/W)
CS
A[2:0]
D[7:0]
RDY
(DTACK)
tSAM
tZD
tDRDY
tACC
VALID ADDRESS
tDD tHA
VALID DATA
tZD
1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM THE FE OF WR TO THE RE OF RDY.
2. tACCFAST REQUIRES A MAXIMUM OF THREE CLK PERIODS AND APPLIES TO A[2:0] = 7, 6, 5, 3, 2, 1
3. tACCMEDIUM REQUIRES A MAXIMUM OF FOUR CLK PERIODS AND APPLIES TO A[2:0] = 4 AND 0 IF THE ACCESS IS TO A CONTROL REGISTER
VERSUS A RAM REGISTER.
4. tACCSLOW REQUIRES A MAXIMUM OF FIVE CLK PERIODS AND APPLIES TO A[2:0] = 0 WHEN ACCESSING RAM REGISTERS.
Figure 6. INM Microport Read Timing Requirements
REV. 0
–5–
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for AD6622 electronic component. |
| Information | Total 28 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ AD6622.PDF Datasheet ] | |
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