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부품번호 AD678 기능
기능 12-Bit 200 kSPS Complete Sampling ADC
제조업체 Analog Devices
로고 Analog Devices 로고


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AD678 데이터시트, 핀배열, 회로
a
FEATURES
AC and DC Characterized and Specified
(K, B and T Grades)
200k Conversions per Second
1 MHz Full Power Bandwidth
500 kHz Full Linear Bandwidth
72 dB S/N+D (K, B, T Grades)
Twos Complement Data Format (Bipolar Mode)
Straight Binary Data Format (Unipolar Mode)
10 MInput Impedance
8-Bit or 16-Bit Bus Interface
On-Board Reference and Clock
10 V Unipolar or Bipolar Input Range
Commercial, Industrial and Military Temperature
Range Grades
MIL-STD-883 Compliant Versions Available
12-Bit 200 kSPS
Complete Sampling ADC
AD678
REFOUT
REFIN
BIPOFF
AIN
AGND
FUNCTIONAL BLOCK DIAGRAM
CS SC OE EOCEN SYNC 12/8 EOC
VOLTAGE
REF.
CONTROL LOGIC
12
12
12-BIT D/A
CONVERSION
CONVERTER
LOGIC
AD678
OUTPUT
REGISTER
SAMPLE/
HOLD
GAIN
STAGE
4
4-BIT FLASH
A/D
CONVERTER
DB11
DB2
DB1
(R/L)
DB0
(HBE)
VCC
VEE
VDD
DGND
PRODUCT DESCRIPTION
The AD678 is a complete, multipurpose 12-bit monolithic
analog-to-digital converter, consisting of a sample-hold ampli-
fier (SHA), a microprocessor compatible bus interface, a voltage
reference and clock generation circuitry.
The AD678 is specified for ac (or “dynamic”) parameters such
as S/N+D ratio, THD and IMD which are important in signal
processing applications. In addition, the AD678K, B and T
grades are fully specified for dc parameters which are important
in measurement applications.
The AD678 offers a choice of digital interface formats; the 12
data bits can be accessed by a 16-bit bus in a single read opera-
tion or by an 8-bit bus in two read operations (8+4), with right
or left justification. Data format is straight binary for unipolar
mode and twos complement binary for bipolar mode. The input
has a full-scale range of 10 V with a full power bandwidth of
1 MHz and a full linear bandwidth of 500 kHz. High input im-
pedance (10 M) allows direct connection to unbuffered
sources without signal degradation.
This product is fabricated on Analog Devices’ BiMOS process,
combining low power CMOS logic with high precision, low
noise bipolar circuits; laser-trimmed thin-film resistors provide
high accuracy. The converter utilizes a recursive subranging
algorithm which includes error correction and flash converter
circuitry to achieve high speed and resolution.
The AD678 operates from +5 V and ±12 V supplies and dissipates
560 mW (typ). The AD678 is available in 28-lead plastic DIP,
ceramic DIP, and 44-lead J-leaded ceramic surface mount packages.
Screening to MIL-STD-883C Class B is also available.
PRODUCT HIGHLIGHTS
1. COMPLETE INTEGRATION: The AD678 minimizes ex-
ternal component requirements by combining a high speed
sample-hold amplifier (SHA), ADC, 5 V reference, clock and
digital interface on a single chip. This provides a fully speci-
fied sampling A/D function unattainable with discrete designs.
2. SPECIFICATIONS: The AD678K, B and T grades provide
fully specified and tested ac and dc parameters. The AD678J,
A and S grades are specified and tested for ac parameters; dc
accuracy specifications are shown as typicals. DC specifica-
tions (such as INL, gain and offset) are important in control
and measurement applications. AC specifications (such as
S/N+D ratio, THD and IMD) are of value in signal process-
ing applications.
3. EASE OF USE: The pinout is designed for easy board lay-
out, and the choice of single or two read cycle output pro-
vides compatibility with 16- or 8-bit buses. Factory trimming
eliminates the need for calibration modes or external trim-
ming to achieve rated performance.
4. RELIABILITY: The AD678 utilizes Analog Devices’ mono-
lithic BiMOS technology. This ensures long-term reliability
compared to multichip and hybrid designs.
5. UPGRADE PATH: The AD678 provides the same pinout as
the 14-bit, 128 kSPS AD679 ADC.
6. The AD678 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD678/883B data sheet for detailed
specifications.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000




AD678 pdf, 반도체, 판매, 대치품
AD678
TIMING SPECIFICATIONS (All grades, TMIN to TMAX, VCC = +12 V ؎ 5%, VEE = –12 V ؎ 5%, VDD = +5 V ؎ 10% unless
otherwise noted)
Parameter
Symbol
Min
Max
SC Delay
Conversion Time
Conversion Ratel
Convert Pulsewidth
Aperture Delay
Status Delay
Access Time2, 3
Float Delay5
Output Delay
Format Setup
OE Delay
Read Pulsewidth
Conversion Delay
EOCEN Delay
tSC
tC
tCR
tCP
tAD
tSD
tBA
tFD
tOD
tFS
tOE
tRP
tCD
tEO
50
3.0 4.4
5
97
5 20
0 400
10 100
10 574
10 80
0
47
0
97
150
0
NOTES
1Includes acquisition time.
2Measured from the falling edge of OE/EOCEN (0.8 V) to the time at which the data lines/EOC cross 2.0 V or 0.8 V. See Figure 3.
3COUT = 100 pF.
4COUT = 50 pF.
5Measured from the rising edge of OE/EOCEN (2.0 V) to the time at which the output voltage changes by 0.5 V. See Figure 3; C OUT = 10 pF.
Specifications subject to change without notice.
Units
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 2. EOC Timing
Figure 1. Conversion Timing
Figure 3. Load Circuit for Bus Timing Specifications
–4– REV. C

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AD678 전자부품, 판매, 대치품
Definition of SpecificationsAD678
NYQUIST FREQUENCY
An implication of the Nyquist sampling theorem, the “Nyquist
Frequency” of a converter is that input frequency which is one-
half the sampling frequency of the converter.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO
S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of a full-scale input signal and is ex-
pressed as a percentage or in decibels. For input signals or
harmonics that are above the Nyquist frequency, the aliased
component is used.
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT
The peak spurious or peak harmonic component is the largest
spectral component excluding the input signal and dc. This
value is expressed in decibels relative to the rms value of a full-
scale input signal.
INTERMODULATION DISTORTION (IMD)
With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products,
of order (m + n), at sum and difference frequencies of mfa ±
nfb, where m, n = 0, 1, 2, 3.... Intermodulation terms are those
for which m or n is not equal to zero. For example, the second
order terms are (fa + fb) and (fa – fb) and the third order terms
are (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb). The IMD
products are expressed as the decibel ratio of the rms sum of
the measured input sides to the rms sum of the distortion terms.
The two signals applied to the converter are of equal ampli-
tude and the peak value of their sum is –0.5 dB from full scale
(9.44 V p-p). The IMD products are normalized to a 0 dB
input signal.
BANDWIDTH
The full-power bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.
The full-linear bandwidth is the input frequency at which the
slew rate limit of the sample-hold-amplifier (SHA) is reached.
At this point, the amplitude of the reconstructed fundamental
has degraded by less than 0.1 dB. Beyond this frequency, distor-
tion of the sampled input signal increases significantly.
The AD678 has been designed to optimize input bandwidth, al-
lowing the AD678 to undersample input signals with frequen-
cies significantly above the converter’s Nyquist frequency.
APERTURE DELAY
Aperture delay is a measure of the SHA’s performance and is
measured from the falling edge of Start Convert (SC) to when
the input signal is held for conversion. In synchronous mode,
Chip Select (CS) should be LOW before SC to minimize aper-
ture delay.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
INPUT SETTLING TIME
Settling time is a function of the SHA’s ability to track fast slew-
ing signals. This is specified as the maximum time required in
track mode after a full-scale step input to guarantee rated con-
version accuracy.
DIFFERENTIAL NONLINEARITY (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes (NMC) are guaranteed.
UNIPOLAR ZERO ERROR
In unipolar mode, the first transition should occur at a level 1/2
LSB above analog ground. Unipolar zero error is the deviation
of the actual transition from that point. This error can be ad-
justed as discussed in the Input Connections and Calibration
section.
BIPOLAR ZERO ERROR
In the bipolar mode, the major carry transition (1111 1111
1111 to 0000 0000 0000) should occur at an analog value 1/2
LSB below analog ground. Bipolar zero error is the deviation of
the actual transition from that point. This error can be adjusted
as discussed in the Input Connections and Calibration section.
GAIN ERROR
The last transition should occur at an analog value 1 1/2 LSB
below the nominal full scale (9.9963 volts for a 0–10 V range,
4.9963 volts for a ± 5 V range). The gain error is the deviation of
the actual difference between the first and last code transition
from the ideal difference between the first and last code transi-
tion. This error can be adjusted as shown in the Input Connec-
tions and Calibration section.
INTEGRAL NONLINEARITY (INL)
The ideal transfer function for a linear ADC is a straight line
drawn between “zero” and “full scale.” The point used as
“zero” occurs 1/2 LSB before the first code transition. “Full
scale” is defined as a level 1 1/2 LSB beyond the last code tran-
sition. Integral nonlinearity is the worst-case deviation of a code
from the straight line. The deviation of each code is measured
from the middle of that code.
POWER SUPPLY REJECTION
Variations in power supply will affect the full-scale transition,
but not the converter’s linearity. Power Supply Rejection is the
maximum change in the full-scale transition point due to a
change in power-supply voltage from the nominal value.
TEMPERATURE DRIFT
This is the maximum change in the parameter from the initial
value (@ +25°C) to the value at TMIN or TMAX.
REV. C
7

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